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| author | Alexander Ivchenko <alexander.ivchenko@intel.com> | 2014-10-14 08:45:17 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2014-10-14 08:45:17 +0000 |
| commit | c305ca7f629af0e4799bf2147967b43eff1dc548 (patch) | |
| tree | 56dd3dd7412f8d99dcb056bd681c56cf1363854c | |
| parent | cf25c30945764f5b0cbdaccb53980bb7132e75bc (diff) | |
| download | gcc-c305ca7f629af0e4799bf2147967b43eff1dc548.zip gcc-c305ca7f629af0e4799bf2147967b43eff1dc548.tar.gz gcc-c305ca7f629af0e4799bf2147967b43eff1dc548.tar.bz2 | |
AVX-512. 70/n. Add vpmaxmin.
gcc/
* config/i386/sse.md
(define_insn "*sse4_1_<code><mode>3<mask_name>"): Add masking.
(define_insn "*sse4_1_<code><mode>3<mask_name>"): Ditto.
Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r216187
| -rw-r--r-- | gcc/ChangeLog | 13 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 28 |
2 files changed, 29 insertions, 12 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4416b51..3516151 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -7,6 +7,19 @@ Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> + * config/i386/sse.md + (define_insn "*sse4_1_<code><mode>3<mask_name>"): Add masking. + (define_insn "*sse4_1_<code><mode>3<mask_name>"): Ditto. + +2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com> + Maxim Kuznetsov <maxim.kuznetsov@intel.com> + Anna Tikhonova <anna.tikhonova@intel.com> + Ilya Tocar <ilya.tocar@intel.com> + Andrey Turetskiy <andrey.turetskiy@intel.com> + Ilya Verbin <ilya.verbin@intel.com> + Kirill Yukhin <kirill.yukhin@intel.com> + Michael Zolotukhin <michael.v.zolotukhin@intel.com> + * config/i386/sse.md (define_insn "avx512bw_umulhrswv32hi3<mask_name>"): New. (define_expand "<ssse3_avx2>_pmulhrsw<mode>3_mask"): Ditto. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 30fc1dc..1de21e4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -10096,15 +10096,17 @@ } }) -(define_insn "*sse4_1_<code><mode>3" - [(set (match_operand:VI14_128 0 "register_operand" "=x,x") +(define_insn "*sse4_1_<code><mode>3<mask_name>" + [(set (match_operand:VI14_128 0 "register_operand" "=x,v") (smaxmin:VI14_128 - (match_operand:VI14_128 1 "nonimmediate_operand" "%0,x") - (match_operand:VI14_128 2 "nonimmediate_operand" "xm,xm")))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + (match_operand:VI14_128 1 "nonimmediate_operand" "%0,v") + (match_operand:VI14_128 2 "nonimmediate_operand" "xm,vm")))] + "TARGET_SSE4_1 + && <mask_mode512bit_condition> + && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "@ p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} - vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" + vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") (set_attr "prefix_extra" "1,*") @@ -10177,15 +10179,17 @@ } }) -(define_insn "*sse4_1_<code><mode>3" - [(set (match_operand:VI24_128 0 "register_operand" "=x,x") +(define_insn "*sse4_1_<code><mode>3<mask_name>" + [(set (match_operand:VI24_128 0 "register_operand" "=x,v") (umaxmin:VI24_128 - (match_operand:VI24_128 1 "nonimmediate_operand" "%0,x") - (match_operand:VI24_128 2 "nonimmediate_operand" "xm,xm")))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + (match_operand:VI24_128 1 "nonimmediate_operand" "%0,v") + (match_operand:VI24_128 2 "nonimmediate_operand" "xm,vm")))] + "TARGET_SSE4_1 + && <mask_mode512bit_condition> + && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "@ p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} - vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" + vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") (set_attr "prefix_extra" "1,*") |