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authorRichard Sandiford <rsandifo@redhat.com>2004-06-25 06:59:03 +0000
committerRichard Sandiford <rsandifo@gcc.gnu.org>2004-06-25 06:59:03 +0000
commitbdb41add9deec358b0724347c73dd2d009ab7f36 (patch)
treedbfcdfed71cfa5741798f5a8c7ed796652e749e4
parent3af5dcdb45192587bb3a338f299d7cc7e7f96125 (diff)
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mips.c (reg_or_const_float_1_operand): Reimplement in terms of const_float_1_operand.
* config/mips/mips.c (reg_or_const_float_1_operand): Reimplement in terms of const_float_1_operand. From-SVN: r83640
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/mips/mips.c19
2 files changed, 8 insertions, 16 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c99ac82..80c7a80 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
2004-06-25 Richard Sandiford <rsandifo@redhat.com>
+ * config/mips/mips.c (reg_or_const_float_1_operand): Reimplement
+ in terms of const_float_1_operand.
+
+2004-06-25 Richard Sandiford <rsandifo@redhat.com>
+
PR target/16144
* config/mips/mips.md (divsf, divdf): Don't FAIL if the first operand
is 1.0; force it into a register instead.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index f481c4b..fe3e66d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1428,26 +1428,13 @@ reg_or_0_operand (rtx op, enum machine_mode mode)
}
}
-/* Accept a register or the floating point constant 1 in the appropriate mode. */
+/* Accept a register or the floating point constant 1 in the
+ appropriate mode. */
int
reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
{
- REAL_VALUE_TYPE d;
-
- switch (GET_CODE (op))
- {
- case CONST_DOUBLE:
- if (mode != GET_MODE (op)
- || (mode != DFmode && mode != SFmode))
- return 0;
-
- REAL_VALUE_FROM_CONST_DOUBLE (d, op);
- return REAL_VALUES_EQUAL (d, dconst1);
-
- default:
- return register_operand (op, mode);
- }
+ return const_float_1_operand (op, mode) || register_operand (op, mode);
}
/* Accept the floating point constant 1 in the appropriate mode. */