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| author | Michael Meissner <meissner@gcc.gnu.org> | 1995-03-01 19:09:39 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 1995-03-01 19:09:39 +0000 |
| commit | bb68ff55b181ac17df6a274b3171876a121fad9d (patch) | |
| tree | 943cc38aa0edd1de772065bd07d29d980cb0d345 | |
| parent | 021035770a2b167047d012c731fbd8be956750f2 (diff) | |
| download | gcc-bb68ff55b181ac17df6a274b3171876a121fad9d.zip gcc-bb68ff55b181ac17df6a274b3171876a121fad9d.tar.gz gcc-bb68ff55b181ac17df6a274b3171876a121fad9d.tar.bz2 | |
Silence warnings on uminsi3, umaxsi3.
From-SVN: r9100
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1b884de..ae27254 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -936,9 +936,9 @@ (define_expand "uminsi3" [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (const_int -2147483648))) + (match_dup 5))) (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") - (const_int -2147483648))) + (match_dup 5))) (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) (const_int 0) (minus:SI (match_dup 4) (match_dup 3)))) @@ -946,13 +946,17 @@ (minus:SI (match_dup 2) (match_dup 3)))] "TARGET_POWER" " -{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") +{ + operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_reg_rtx (SImode); + operands[5] = GEN_INT (-2147483647 - 1); +}") (define_expand "umaxsi3" [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (const_int -2147483648))) + (match_dup 5))) (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") - (const_int -2147483648))) + (match_dup 5))) (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) (const_int 0) (minus:SI (match_dup 4) (match_dup 3)))) @@ -960,7 +964,11 @@ (plus:SI (match_dup 3) (match_dup 1)))] "TARGET_POWER" " -{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") +{ + operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_reg_rtx (SImode); + operands[5] = GEN_INT (-2147483647 - 1); +}") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |