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| author | Alexander Ivchenko <alexander.ivchenko@intel.com> | 2014-10-14 08:35:12 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2014-10-14 08:35:12 +0000 |
| commit | b99ba39a8470a3641e04463b0971a0f9eb4aaa5a (patch) | |
| tree | 26498ac45e042da355a219ee43b5e181a6b127e1 | |
| parent | 2ac7a566e85dfe93e57db70410a7f6045387efa1 (diff) | |
| download | gcc-b99ba39a8470a3641e04463b0971a0f9eb4aaa5a.zip gcc-b99ba39a8470a3641e04463b0971a0f9eb4aaa5a.tar.gz gcc-b99ba39a8470a3641e04463b0971a0f9eb4aaa5a.tar.bz2 | |
AVX-512. 66/n. Extend vpalignr insn patterns.
gcc/
* config/i386/sse.md
(define_mode_iterator SSESCALARMODE): Add V4TI mode.
(define_insn "<ssse3_avx2>_palignr<mode>_mask"): New.
(define_insn "<ssse3_avx2>_palignr<mode>"): Add EVEX version.
Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r216183
| -rw-r--r-- | gcc/ChangeLog | 14 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 30 |
2 files changed, 40 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 646ec01..6553b21 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -8,6 +8,20 @@ Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/i386/sse.md + (define_mode_iterator SSESCALARMODE): Add V4TI mode. + (define_insn "<ssse3_avx2>_palignr<mode>_mask"): New. + (define_insn "<ssse3_avx2>_palignr<mode>"): Add EVEX version. + +2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com> + Maxim Kuznetsov <maxim.kuznetsov@intel.com> + Anna Tikhonova <anna.tikhonova@intel.com> + Ilya Tocar <ilya.tocar@intel.com> + Andrey Turetskiy <andrey.turetskiy@intel.com> + Ilya Verbin <ilya.verbin@intel.com> + Kirill Yukhin <kirill.yukhin@intel.com> + Michael Zolotukhin <michael.v.zolotukhin@intel.com> + + * config/i386/sse.md (define_expand "mul<mode>3<mask_name>"): Add masking. 2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 18614ca..135cb04 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -350,7 +350,7 @@ ;; ??? This should probably be dropped in favor of VIMAX_AVX2. (define_mode_iterator SSESCALARMODE - [(V2TI "TARGET_AVX2") TI]) + [(V4TI "TARGET_AVX512BW") (V2TI "TARGET_AVX2") TI]) (define_mode_iterator VI12_AVX2 [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI @@ -13455,11 +13455,33 @@ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set_attr "mode" "DI")]) +(define_insn "<ssse3_avx2>_palignr<mode>_mask" + [(set (match_operand:VI1_AVX2 0 "register_operand" "=v") + (vec_merge:VI1_AVX2 + (unspec:VI1_AVX2 + [(match_operand:VI1_AVX2 1 "register_operand" "v") + (match_operand:VI1_AVX2 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")] + UNSPEC_PALIGNR) + (match_operand:VI1_AVX2 4 "vector_move_operand" "0C") + (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))] + "TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)" +{ + operands[3] = GEN_INT (INTVAL (operands[3]) / 8); + return "vpalignr\t{%3, %2, %1, %0%{%5%}%N4|%0%{%5%}%N4, %1, %2, %3}"; +} + [(set_attr "type" "sseishft") + (set_attr "atom_unit" "sishuf") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + (define_insn "<ssse3_avx2>_palignr<mode>" - [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x") + [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,v") (unspec:SSESCALARMODE - [(match_operand:SSESCALARMODE 1 "register_operand" "0,x") - (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,xm") + [(match_operand:SSESCALARMODE 1 "register_operand" "0,v") + (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,vm") (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")] UNSPEC_PALIGNR))] "TARGET_SSSE3" |