(fsel): Remove insns with record bit set.

From-SVN: r6435

1 files changed, 6 insertions, 56 deletions

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b4d29c5..7c5388f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2349,35 +2349,6 @@
   "fsel %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
-(define_insn ""
-  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-	(compare:CCFP
-	 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
-			      (const_int 0))
-			  (match_operand:SF 2 "gpc_reg_operand" "f")
-			  (match_operand:SF 3 "gpc_reg_operand" "f"))
-	 (const_int 0)))
-   (clobber (match_scratch:SF 4 "=f"))]
-  "TARGET_PPCFPX"
-  "fsel. %4,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:CCFP 4 "cc_reg_operand" "=y")
-	(compare:CCFP
-	 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
-			      (const_int 0))
-			  (match_operand:SF 2 "gpc_reg_operand" "f")
-			  (match_operand:SF 3 "gpc_reg_operand" "f"))
-	 (const_int 0)))
-   (set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(if_then_else:SF (ge (match_dup 1) (const_int 0))
-			 (match_dup 2)
-			 (match_dup 3)))]
-  "TARGET_PPCFPX"
-  "fsel. %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
 (define_insn "negdf2"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
@@ -2473,10 +2444,12 @@
   "TARGET_PPCFPX || TARGET_POWER2"
   "fsqrt %0,%1"
   [(set_attr "type" "dsqrt")])
+
 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel
 ;; instruction and some auxiliary computations.  Then we just have a single
 ;; DEFINE_INSN for fsel and the define_splits to make them if made by
 ;; combine.
+
 (define_expand "maxdf3"
   [(set (match_dup 3)
 	(minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
@@ -2489,6 +2462,7 @@
   "TARGET_PPCFPX"
   "
 { operands[3] = gen_reg_rtx (DFmode); }")
+
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
 	(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
@@ -2503,6 +2477,7 @@
 			 (match_dup 1)
 			 (match_dup 2)))]
   "")
+
 (define_expand "mindf3"
   [(set (match_dup 3)
 	(minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
@@ -2515,6 +2490,7 @@
   "TARGET_PPCFPX"
   "
 { operands[3] = gen_reg_rtx (DFmode); }")
+
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
 	(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
@@ -2529,6 +2505,7 @@
 			 (match_dup 1)
 			 (match_dup 2)))]
   "")
+
 (define_insn ""
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
@@ -2538,33 +2515,6 @@
   "TARGET_PPCFPX"
   "fsel %0,%1,%2,%3"
   [(set_attr "type" "fp")])
-(define_insn ""
-  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-	(compare:CCFP
-	 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
-			      (const_int 0))
-			  (match_operand:DF 2 "gpc_reg_operand" "f")
-			  (match_operand:DF 3 "gpc_reg_operand" "f"))
-	 (const_int 0)))
-   (clobber (match_scratch:DF 4 "=f"))]
-  "TARGET_PPCFPX"
-  "fsel. %4,%1,%2,%3"
-  [(set_attr "type" "fp")])
-(define_insn ""
-  [(set (match_operand:CCFP 4 "cc_reg_operand" "=y")
-	(compare:CCFP
-	 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
-			      (const_int 0))
-			  (match_operand:DF 2 "gpc_reg_operand" "f")
-			  (match_operand:DF 3 "gpc_reg_operand" "f"))
-	 (const_int 0)))
-   (set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(if_then_else:DF (ge (match_dup 1) (const_int 0))
-			 (match_dup 2)
-			 (match_dup 3)))]
-  "TARGET_PPCFPX"
-  "fsel. %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
 
 ;; Conversions to and from floating-point.
 (define_expand "floatsidf2"