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| author | Ulrich Weigand <uweigand@de.ibm.com> | 2011-10-21 01:27:36 +0000 |
|---|---|---|
| committer | Ulrich Weigand <uweigand@gcc.gnu.org> | 2011-10-21 01:27:36 +0000 |
| commit | b66cf46e4d410cb19a3529efa2ffda289848298d (patch) | |
| tree | 957c6c40ee40385030690d332b7b1c12a97926bb | |
| parent | d2a80c9fbd5e17f2923dbe9f84dea940e5f540e7 (diff) | |
| download | gcc-b66cf46e4d410cb19a3529efa2ffda289848298d.zip gcc-b66cf46e4d410cb19a3529efa2ffda289848298d.tar.gz gcc-b66cf46e4d410cb19a3529efa2ffda289848298d.tar.bz2 | |
spu.md ("vec_permv16qi"): Reduce selector modulo 32 before using the shufb instruction.
* config/spu/spu.md ("vec_permv16qi"): Reduce selector modulo 32
before using the shufb instruction.
From-SVN: r180283
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/spu/spu.md | 12 |
2 files changed, 14 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 30a25f9..3b5fc23 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2011-10-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> + + * config/spu/spu.md ("vec_permv16qi"): Reduce selector modulo 32 + before using the shufb instruction. + 2011-10-20 Kirill Yukhin <kirill.yukhin@intel.com> PR target/50766 diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md index 00cfaa4..ca2cad9b 100644 --- a/gcc/config/spu/spu.md +++ b/gcc/config/spu/spu.md @@ -4395,16 +4395,22 @@ selb\t%0,%4,%0,%3" "shufb\t%0,%1,%2,%3" [(set_attr "type" "shuf")]) +; The semantics of vec_permv16qi are nearly identical to those of the SPU +; shufb instruction, except that we need to reduce the selector modulo 32. (define_expand "vec_permv16qi" - [(set (match_operand:V16QI 0 "spu_reg_operand" "") + [(set (match_dup 4) (and:V16QI (match_operand:V16QI 3 "spu_reg_operand" "") + (match_dup 6))) + (set (match_operand:V16QI 0 "spu_reg_operand" "") (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "") (match_operand:V16QI 2 "spu_reg_operand" "") - (match_operand:V16QI 3 "spu_reg_operand" "")] + (match_dup 5)] UNSPEC_SHUFB))] "" { - operands[3] = gen_lowpart (TImode, operands[3]); + operands[4] = gen_reg_rtx (V16QImode); + operands[5] = gen_lowpart (TImode, operands[4]); + operands[6] = spu_const (V16QImode, 31); }) (define_insn "nop" |