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| author | Richard Earnshaw <rearnsha@arm.com> | 2017-07-13 10:01:55 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2017-07-13 10:01:55 +0000 |
| commit | b663b8319ded32fe3fb8224dae71792af88f87fe (patch) | |
| tree | 597da83f41179a5ef818fcc864bb40acf2954d00 | |
| parent | 8f4956cadfef8fd4f43fecca65070428a504188d (diff) | |
| download | gcc-b663b8319ded32fe3fb8224dae71792af88f87fe.zip gcc-b663b8319ded32fe3fb8224dae71792af88f87fe.tar.gz gcc-b663b8319ded32fe3fb8224dae71792af88f87fe.tar.bz2 | |
[ARM, VXworks] Fix build
My patch last week to address selection of be8 linking mode broke the
build for vxworks. It turns out that this port is one of the few
remaining that is still not based on the EABI/AAPCS.
This patch fixes the build, but I've not really tested it beyond
building the core compiler binaries. Building a workable compiler
entails downloading a load of vxworks stuff that I'm not sure where to
find.
* config/arm/vxworks.h (TARGET_ENDIAN_DEFAULT): Define.
From-SVN: r250177
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/arm/vxworks.h | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4f7907a..5bd9387 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2017-07-13 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/vxworks.h (TARGET_ENDIAN_DEFAULT): Define. + 2017-07-13 Maxim Ostapenko <m.ostapenko@samsung.com> * asan.c (asan_emit_allocas_unpoison): Use ptr_mode for arguments diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h index 9af37c7..f20324f 100644 --- a/gcc/config/arm/vxworks.h +++ b/gcc/config/arm/vxworks.h @@ -117,3 +117,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* This platform supports the probing method of stack checking (RTP mode). 8K is reserved in the stack to propagate exceptions in case of overflow. */ #define STACK_CHECK_PROTECT 8192 + +/* Unless overridded by the target options, the default is little-endian. */ +#define TARGET_ENDIAN_DEFAULT 0 |