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| author | Ilya Enkovich <enkovich.gnu@gmail.com> | 2016-03-31 15:37:12 +0000 |
|---|---|---|
| committer | Ilya Enkovich <ienkovich@gcc.gnu.org> | 2016-03-31 15:37:12 +0000 |
| commit | b660f9ec7e8b9dbdc1bbeafc62889e596458791a (patch) | |
| tree | e7b1c1abfec3cbf8fe3ada56c37626ae56345edf | |
| parent | 88504f3435845976b92ee7e9d358f8e687502772 (diff) | |
| download | gcc-b660f9ec7e8b9dbdc1bbeafc62889e596458791a.zip gcc-b660f9ec7e8b9dbdc1bbeafc62889e596458791a.tar.gz gcc-b660f9ec7e8b9dbdc1bbeafc62889e596458791a.tar.bz2 | |
re PR target/70442 (gcc ICE at -O2 and above on valid code on x86_64-linux-gnu in "extract_insn")
gcc/
PR target/70442
* config/i386/i386.c (scalar_chain::convert_op): Fix
description.
(scalar_chain::convert_insn): Call convert_op for reg
moves to handle undefined registers.
gcc/testsuite/
PR target/70442
* gcc.dg/pr70442.c: New test.
From-SVN: r234637
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 9 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr70442.c | 20 |
4 files changed, 39 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c58b659..28ff732 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2016-03-31 Ilya Enkovich <enkovich.gnu@gmail.com> + + PR target/70442 + * config/i386/i386.c (scalar_chain::convert_op): Fix + description. + (scalar_chain::convert_insn): Call convert_op for reg + moves to handle undefined registers. + 2016-03-31 Nathan Sidwell <nathan@acm.org> PR c++/70393 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 7a75a31..e5dfb950 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3384,9 +3384,10 @@ scalar_chain::convert_reg (unsigned regno) BITMAP_FREE (conv); } -/* Convert operand OP in INSN. All register uses - are converted during registers conversion. - Therefore we should just handle memory operands. */ +/* Convert operand OP in INSN. We should handle + memory operands and uninitialized registers. + All other register uses are converted during + registers conversion. */ void scalar_chain::convert_op (rtx *op, rtx_insn *insn) @@ -3467,6 +3468,8 @@ scalar_chain::convert_insn (rtx_insn *insn) break; case REG: + if (!MEM_P (dst)) + convert_op (&src, insn); break; case SUBREG: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f977fc8..ec0b95a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-03-31 Ilya Enkovich <enkovich.gnu@gmail.com> + + PR target/70442 + * gcc.dg/pr70442.c: New test. + 2016-03-31 Nathan Sidwell <nathan@acm.org> PR c++/70393 diff --git a/gcc/testsuite/gcc.dg/pr70442.c b/gcc/testsuite/gcc.dg/pr70442.c new file mode 100644 index 0000000..b9c11ea --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr70442.c @@ -0,0 +1,20 @@ +/* PR target/70442 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-msse2" { target ia32 } } */ + +char a, c; +void +fn1 () +{ + long long b; + long m; + int d; + switch (d) + { + case 5: + b = a; + } + b ^= m; + c = b >> b; +} |