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| author | Peixin Qiao <qiaopeixin@huawei.com> | 2020-08-12 17:11:41 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-08-12 17:11:41 +0100 |
| commit | b418ccb358e428091fb9c6020fd10be5ae40a17a (patch) | |
| tree | d1a0e7ac1cc37fb49f6c34184d9df44c4eca2f4b | |
| parent | 21cfe724cbdc30612bf1ef59b26f19ada2210832 (diff) | |
| download | gcc-b418ccb358e428091fb9c6020fd10be5ae40a17a.zip gcc-b418ccb358e428091fb9c6020fd10be5ae40a17a.tar.gz gcc-b418ccb358e428091fb9c6020fd10be5ae40a17a.tar.bz2 | |
AArch64: Add if condition in aarch64_function_value [PR96479]
Report diagnostic information instead of ICE if it generats fp/simd for
return register when fp/simd is disabled by -mgeneral-regs-only.
gcc/ChangeLog:
* config/aarch64/aarch64.c (aarch64_function_value): Add if
condition to check ag_mode after entering if condition of
aarch64_vfp_is_call_or_return_candidate. If TARGET_FLOAT is
set as false by -mgeneral-regs-only, report the diagnostic
information of -mgeneral-regs-only imcompatible with the use
of fp/simd register(s).
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/mgeneral-regs_1.c: Add the comment that
-mgeneral-regs-only is compatible with the use of vector type
used in the test case.
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/mgeneral-regs_1.c | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index b7f5bc7..f80594d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5554,6 +5554,10 @@ aarch64_function_value (const_tree type, const_tree func, if (aarch64_vfp_is_call_or_return_candidate (mode, type, &ag_mode, &count, NULL, false)) { + /* TYPE passed in fp/simd registers. */ + if (!TARGET_FLOAT) + aarch64_err_no_fpadvsimd (ag_mode); + gcc_assert (!sve_p); if (!aarch64_composite_type_p (type, mode)) { diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_1.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_1.c index 336402e..6f785c9 100644 --- a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_1.c +++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_1.c @@ -4,6 +4,6 @@ typedef int int32x2_t __attribute__ ((__vector_size__ ((8)))); /* { dg-error "'-mgeneral-regs-only' is incompatible with the use of vector types" "" {target "aarch64*-*-*"} .+1 } */ int32x2_t test (int32x2_t a, int32x2_t b) -{ - return a + b; +{ /* { dg-error "'-mgeneral-regs-only' is incompatible with the use of vector types" } */ + return a + b; /* { dg-error "'-mgeneral-regs-only' is incompatible with the use of vector types" } */ } |