diff options
| author | Richard Earnshaw <rearnsha@arm.com> | 2005-11-18 17:59:37 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2005-11-18 17:59:37 +0000 |
| commit | a6a5de042872e3892f20225d1e5a10ca7bc2c990 (patch) | |
| tree | 363047f85f3f0503fd059d35803a91e342638058 | |
| parent | e5e0238e33f171d850971b3c982d31e5aaf2265d (diff) | |
| download | gcc-a6a5de042872e3892f20225d1e5a10ca7bc2c990.zip gcc-a6a5de042872e3892f20225d1e5a10ca7bc2c990.tar.gz gcc-a6a5de042872e3892f20225d1e5a10ca7bc2c990.tar.bz2 | |
re PR target/24914 (gcc fails when built with --with-cpu=ep9312 --with-fpu=maverick)
PR target/24914
* arm.c (arm_hard_regno_mode_ok): Co-processor registers aren't ok
when not generating code to use that co-processor.
From-SVN: r107187
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 32 |
2 files changed, 26 insertions, 12 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 82b5cb8..031402b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2005-11-18 Richard Earnshaw <richard.earnshaw@arm.com> + + PR target/24914 + * arm.c (arm_hard_regno_mode_ok): Co-processor registers aren't ok + when not generating code to use that co-processor. + 2005-11-18 James A. Morrison <phython@gcc.gnu.org> * tree-flow.h (reserve_phi_args_for_new_edge, create_phi_node, diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b2fad56..6165545 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -11818,7 +11818,9 @@ int arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) { if (GET_MODE_CLASS (mode) == MODE_CC) - return regno == CC_REGNUM || regno == VFPCC_REGNUM; + return (regno == CC_REGNUM + || (TARGET_HARD_FLOAT && TARGET_VFP + && regno == VFPCC_REGNUM)); if (TARGET_THUMB) /* For the Thumb we only allow values bigger than SImode in @@ -11828,7 +11830,8 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) start of an even numbered register pair. */ return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); - if (IS_CIRRUS_REGNUM (regno)) + if (TARGET_HARD_FLOAT && TARGET_MAVERICK + && IS_CIRRUS_REGNUM (regno)) /* We have outlawed SI values in Cirrus registers because they reside in the lower 32 bits, but SF values reside in the upper 32 bits. This causes gcc all sorts of grief. We can't @@ -11836,7 +11839,8 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) get sign extended to 64bits-- aldyh. */ return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); - if (IS_VFP_REGNUM (regno)) + if (TARGET_HARD_FLOAT && TARGET_VFP + && IS_VFP_REGNUM (regno)) { if (mode == SFmode || mode == SImode) return TRUE; @@ -11847,28 +11851,32 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) return FALSE; } - if (IS_IWMMXT_GR_REGNUM (regno)) - return mode == SImode; - - if (IS_IWMMXT_REGNUM (regno)) - return VALID_IWMMXT_REG_MODE (mode); + if (TARGET_REALLY_IWMMXT) + { + if (IS_IWMMXT_GR_REGNUM (regno)) + return mode == SImode; + if (IS_IWMMXT_REGNUM (regno)) + return VALID_IWMMXT_REG_MODE (mode); + } + /* We allow any value to be stored in the general registers. Restrict doubleword quantities to even register pairs so that we can use ldrd. */ if (regno <= LAST_ARM_REGNUM) return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); - if ( regno == FRAME_POINTER_REGNUM + if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) /* We only allow integers in the fake hard registers. */ return GET_MODE_CLASS (mode) == MODE_INT; /* The only registers left are the FPA registers which we only allow to hold FP values. */ - return GET_MODE_CLASS (mode) == MODE_FLOAT - && regno >= FIRST_FPA_REGNUM - && regno <= LAST_FPA_REGNUM; + return (TARGET_HARD_FLOAT && TARGET_FPA + && GET_MODE_CLASS (mode) == MODE_FLOAT + && regno >= FIRST_FPA_REGNUM + && regno <= LAST_FPA_REGNUM); } int |