(define_function_unit): Remove ppc604 from sqrt list.

(divsi3, udivsi3): Remove spaces from PowerPC output templates.
(sqrtsf2, maxsf3, minsf3, sqrtdf2, maxdf3, mindf3): Use new macros.
(floatdidf2, fix_truncdfdi2, ffsdi2, muldi3, smuldi3_highpart,
umuldi3_highpart, divdi3, udivdi3, rotldi3): New patterns.
(movdi): Handle moves between FPRs and GPRs.
(scc insn): Correct swapped compare and delayed_compare attributes.

From-SVN: r7430

1 files changed, 139 insertions, 19 deletions

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1872dff..c4f48d1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -221,12 +221,12 @@
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "ssqrt")
-       (eq_attr "cpu" "ppc604,ppc620"))
+       (eq_attr "cpu" "ppc620"))
   31 31)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "dsqrt")
-       (eq_attr "cpu" "ppc604,ppc620"))
+       (eq_attr "cpu" "ppc620"))
   31 31)
 
 ; RIOS2 has two symmetric FPUs.
@@ -1164,7 +1164,7 @@
         (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                 (match_operand:SI 2 "gpc_reg_operand" "r")))]
   "TARGET_POWERPC"
-  "divw %0, %1, %2"
+  "divw %0,%1,%2"
   [(set_attr "type" "idiv")])
 
 (define_expand "udivsi3"
@@ -1189,7 +1189,7 @@
         (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                  (match_operand:SI 2 "gpc_reg_operand" "r")))]
   "TARGET_POWERPC"
-  "divwu %0, %1, %2"
+  "divwu %0,%1,%2"
   [(set_attr "type" "idiv")])
 
 ;; For powers of two we can do srai/aze for divide and then adjust for
@@ -2713,13 +2713,13 @@
 (define_expand "sqrtsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
 	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "TARGET_PPCFPX || TARGET_POWER2"
+  "TARGET_PPC_GPOPT || TARGET_POWER2"
   "")
 
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GPOPT"
   "fsqrts %0,%1"
   [(set_attr "type" "ssqrt")])
 
@@ -2743,7 +2743,7 @@
 			     (const_int 0))
 			 (match_dup 1)
 			 (match_dup 2)))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   "
 { operands[3] = gen_reg_rtx (SFmode); }")
 
@@ -2752,7 +2752,7 @@
 	(smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
 		 (match_operand:SF 2 "reg_or_short_operand" "")))
    (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   [(set (match_dup 3)
 	(minus:SF (match_dup 1) (match_dup 2)))
    (set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -2771,7 +2771,7 @@
 			     (const_int 0))
 			 (match_dup 1)
 			 (match_dup 2)))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   "
 { operands[3] = gen_reg_rtx (SFmode); }")
 
@@ -2780,7 +2780,7 @@
 	(smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
 		 (match_operand:SF 2 "reg_or_short_operand" "")))
    (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   [(set (match_dup 3)
 	(minus:SF (match_dup 2) (match_dup 1)))
    (set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -2796,7 +2796,7 @@
 			     (const_int 0))
 			 (match_operand:SF 2 "gpc_reg_operand" "f")
 			 (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   "fsel %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
@@ -2892,7 +2892,7 @@
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
-  "TARGET_PPCFPX || TARGET_POWER2"
+  "TARGET_PPC_GPOPT || TARGET_POWER2"
   "fsqrt %0,%1"
   [(set_attr "type" "dsqrt")])
 
@@ -2910,7 +2910,7 @@
 			     (const_int 0))
 			 (match_dup 1)
 			 (match_dup 2)))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   "
 { operands[3] = gen_reg_rtx (DFmode); }")
 
@@ -2919,7 +2919,7 @@
 	(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
 		 (match_operand:DF 2 "reg_or_short_operand" "")))
    (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   [(set (match_dup 3)
 	(minus:DF (match_dup 1) (match_dup 2)))
    (set (match_operand:DF 0 "gpc_reg_operand" "")
@@ -2938,7 +2938,7 @@
 			     (const_int 0))
 			 (match_dup 1)
 			 (match_dup 2)))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   "
 { operands[3] = gen_reg_rtx (DFmode); }")
 
@@ -2947,7 +2947,7 @@
 	(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
 		 (match_operand:DF 2 "reg_or_short_operand" "")))
    (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   [(set (match_dup 3)
 	(minus:DF (match_dup 2) (match_dup 1)))
    (set (match_operand:DF 0 "gpc_reg_operand" "")
@@ -2963,7 +2963,7 @@
 			     (const_int 0))
 			 (match_operand:DF 2 "gpc_reg_operand" "f")
 			 (match_operand:DF 3 "gpc_reg_operand" "f")))]
-  "TARGET_PPCFPX"
+  "TARGET_PPC_GFXOPT"
   "fsel %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
@@ -3159,6 +3159,20 @@
 { 
   rs6000_trunc_used = 1;
 }")
+
+(define_insn "floatdidf2"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
+  "TARGET_POWERPC64"
+  "fcfid %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "fix_truncdfdi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+	(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
+  "TARGET_POWERPC64"
+  "fctidz %0,%1"
+  [(set_attr "type" "fp")])
 
 ;; Define the DImode operations that can be done in a small number
 ;; of instructions.
@@ -3375,7 +3389,7 @@
 ;; just handle shifts by constants.
 
 (define_expand "ashrdi3"
-  [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
+  [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")
 		   (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
 				(match_operand:SI 2 "general_operand" "")))
 	      (clobber (match_scratch:SI 3 ""))])]
@@ -3396,6 +3410,91 @@
    sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
   [(set_attr "length" "8")])
 
+;; PowerPC64 DImode operations.
+
+(define_insn "ffsdi2"
+  [(set (match_operand:DI 0 "register_operand" "=&r")
+	(ffs:DI (match_operand:DI 1 "register_operand" "r")))]
+  "TARGET_POWERPC64"
+  "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
+  [(set_attr "length" "16")])
+
+(define_insn "muldi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+		 (match_operand:DI 2 "reg_or_short_operand" "r")))]
+  "TARGET_POWERPC64"
+  "mulld %0,%1,%2"
+   [(set_attr "type" "imul")])
+
+(define_insn "smuldi3_highpart"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(truncate:DI
+	 (lshiftrt:TI (mult:TI (sign_extend:TI
+				(match_operand:DI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:TI
+				(match_operand:DI 2 "gpc_reg_operand" "r")))
+		      (const_int 64))))]
+  "TARGET_POWERPC64"
+  "mulhd %0,%1,%2"
+  [(set_attr "type" "imul")])
+
+(define_insn "umuldi3_highpart"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(truncate:DI
+	 (lshiftrt:TI (mult:TI (zero_extend:TI
+				(match_operand:DI 1 "gpc_reg_operand" "%r"))
+			       (zero_extend:TI
+				(match_operand:DI 2 "gpc_reg_operand" "r")))
+		      (const_int 64))))]
+  "TARGET_POWERPC64"
+  "mulhdu %0,%1,%2"
+  [(set_attr "type" "imul")])
+
+(define_insn "divdi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+        (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+                 (match_operand:DI 2 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC64"
+  "divd %0,%1,%2"
+  [(set_attr "type" "idiv")])
+
+(define_insn "udivdi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+        (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+                 (match_operand:DI 2 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC64"
+  "divdu %0,%1,%2"
+  [(set_attr "type" "idiv")])
+
+(define_insn "rotldi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		   (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
+  "TARGET_POWERPC64"
+  "rld%I2cl %0,%1,%h2,0")
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			       (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+		    (const_int 0)))
+   (clobber (match_scratch:DI 3 "=r"))]
+  "TARGET_POWERPC64"
+  "rld%I2cl. %3,%1,%h2,0"
+  [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			       (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+		    (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(rotate:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC64"
+  "rld%I2cl. %0,%1,%h2,0"
+  [(set_attr "type" "delayed_compare")])
+
 ;; Now define ways of moving data around.
 ;;
 ;; For SI, we special-case integers that can't be loaded in one insn.  We
@@ -3869,6 +3968,27 @@
 
   if (GET_CODE (operands[0]) == MEM)
     operands[1] = force_reg (DImode, operands[1]);
+
+      /* Stores between FPR and any non-FPR registers must go through a
+         temporary stack slot.  */
+
+  if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
+      && ((FP_REGNO_P (REGNO (operands[0]))
+	   && ! FP_REGNO_P (REGNO (operands[1])))
+	  || (FP_REGNO_P (REGNO (operands[1]))
+	      && ! FP_REGNO_P (REGNO (operands[0])))))
+    {
+      rtx stack_slot;
+
+      if (reload_in_progress)
+	stack_slot = gen_rtx (MEM, DImode,
+			      plus_constant (stack_pointer_rtx, 8));
+      else
+	stack_slot = assign_stack_temp (DImode, 8, 0);
+      emit_move_insn (stack_slot, operands[1]);
+      emit_move_insn (operands[0], stack_slot);
+      DONE;
+    }
 }")
 
 (define_insn ""
@@ -5339,7 +5459,7 @@
   "@
    doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
    {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
-  [(set_attr "type" "delayed_compare,compare")
+  [(set_attr "type" "compare,delayed_compare")
    (set_attr "length" "12")])
 
 (define_insn ""