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authorDJ Delorie <dj@redhat.com>2009-07-01 16:07:41 -0400
committerDJ Delorie <dj@gcc.gnu.org>2009-07-01 16:07:41 -0400
commita12e9a5f69691674a10bf15f3d75df5e472b7181 (patch)
tree872cc37fcb82252dadeaa2d680074e87d8e4e466
parent2a5bd62a7f71759e66631b7c89ea445ad8108df1 (diff)
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mep-ivc2.cpu (cmov, [...]): Add intrinsic names to VLIW variants.
* config/mep/mep-ivc2.cpu (cmov, cmovc, cmovh): Add intrinsic names to VLIW variants. (ivc2rm, ivc2crn): Make data type consistent with non-VLIW variants. * config/mep/intrinsics.md: Regenerate. * config/mep/intrinsics.h: Regenerate. * config/mep/mep-intrin.h: Regenerate. From-SVN: r149151
Diffstat
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/mep/intrinsics.h6
-rw-r--r--gcc/config/mep/intrinsics.md626
-rw-r--r--gcc/config/mep/mep-intrin.h588
-rw-r--r--gcc/config/mep/mep-ivc2.cpu16
5 files changed, 620 insertions, 624 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c71f379..cdcc269 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2009-07-01 DJ Delorie <dj@redhat.com>
+
+ * config/mep/mep-ivc2.cpu (cmov, cmovc, cmovh): Add intrinsic names to VLIW variants.
+ (ivc2rm, ivc2crn): Make data type consistent with non-VLIW variants.
+ * config/mep/intrinsics.md: Regenerate.
+ * config/mep/intrinsics.h: Regenerate.
+ * config/mep/mep-intrin.h: Regenerate.
+
2009-07-01 Jakub Jelinek <jakub@redhat.com>
PR debug/40462
diff --git a/gcc/config/mep/intrinsics.h b/gcc/config/mep/intrinsics.h
index e1b30e5..ea4c871 100644
--- a/gcc/config/mep/intrinsics.h
+++ b/gcc/config/mep/intrinsics.h
@@ -409,12 +409,6 @@ cp_data_bus_int mep_cdadd3 (cp_data_bus_int, cp_data_bus_int);
cp_v2si mep_cpadd3_w (cp_v2si, cp_v2si);
cp_v4hi mep_cpadd3_h (cp_v4hi, cp_v4hi);
cp_v8qi mep_cpadd3_b (cp_v8qi, cp_v8qi);
-void mep_cmovh_rn_crm_p0 (long, long); // volatile
-void mep_cmovh_crn_rm_p0 (long, long); // volatile
-void mep_cmovc_rn_ccrm_p0 (long, long); // volatile
-void mep_cmovc_ccrn_rm_p0 (long, long); // volatile
-void mep_cmov_rn_crm_p0 (long, long); // volatile
-void mep_cmov_crn_rm_p0 (long, long); // volatile
void mep_bsrv (void *);
void mep_jsrv (long);
void mep_synccp (); // volatile
diff --git a/gcc/config/mep/intrinsics.md b/gcc/config/mep/intrinsics.md
index aa036f8..756f555 100644
--- a/gcc/config/mep/intrinsics.md
+++ b/gcc/config/mep/intrinsics.md
@@ -24781,7 +24781,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=x")
(unspec:DI [
(match_operand:DI 1 "general_operand" "x")
- ] 4184))]
+ ] 4172))]
"CGEN_ENABLE_INSN_P (648)"
"cpmov\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -24796,7 +24796,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=x")
(unspec:DI [
(match_operand:DI 1 "general_operand" "x")
- ] 4184))]
+ ] 4172))]
"CGEN_ENABLE_INSN_P (649)"
"cpmov\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25224,7 +25224,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:DI 1 "general_operand" "x")
- ] 4168))]
+ ] 4156))]
"CGEN_ENABLE_INSN_P (676)"
"cmovh\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25237,9 +25237,9 @@
(define_insn "cgen_intrinsic_cmovh_rn_crm_p0"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
- (unspec_volatile:SI [
+ (unspec:SI [
(match_operand:DI 1 "general_operand" "x")
- ] 3556))]
+ ] 4156))]
"CGEN_ENABLE_INSN_P (677)"
"cmovh\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25255,7 +25255,7 @@
(unspec:DI [
(match_operand:DI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 4170))]
+ ] 4158))]
"CGEN_ENABLE_INSN_P (678)"
"cmovh\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -25268,10 +25268,10 @@
(define_insn "cgen_intrinsic_cmovh_crn_rm_p0"
[(set (match_operand:DI 0 "nonimmediate_operand" "=x")
- (unspec_volatile:DI [
+ (unspec:DI [
(match_operand:DI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3558))]
+ ] 4158))]
"CGEN_ENABLE_INSN_P (679)"
"cmovh\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -25286,7 +25286,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec_volatile:SI [
(match_operand:SI 1 "general_operand" "y")
- ] 4172))]
+ ] 4160))]
"CGEN_ENABLE_INSN_P (680)"
"cmovc\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25301,7 +25301,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec_volatile:SI [
(match_operand:SI 1 "general_operand" "y")
- ] 3560))]
+ ] 4160))]
"CGEN_ENABLE_INSN_P (681)"
"cmovc\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25316,7 +25316,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=y")
(unspec_volatile:SI [
(match_operand:SI 1 "general_operand" "r")
- ] 4174))]
+ ] 4162))]
"CGEN_ENABLE_INSN_P (682)"
"cmovc\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25331,7 +25331,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=y")
(unspec_volatile:SI [
(match_operand:SI 1 "general_operand" "r")
- ] 3562))]
+ ] 4162))]
"CGEN_ENABLE_INSN_P (683)"
"cmovc\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25346,7 +25346,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:DI 1 "general_operand" "x")
- ] 4176))]
+ ] 4164))]
"CGEN_ENABLE_INSN_P (684)"
"cmov\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25359,9 +25359,9 @@
(define_insn "cgen_intrinsic_cmov_rn_crm_p0"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
- (unspec_volatile:SI [
+ (unspec:SI [
(match_operand:DI 1 "general_operand" "x")
- ] 3564))]
+ ] 4164))]
"CGEN_ENABLE_INSN_P (685)"
"cmov\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25377,7 +25377,7 @@
(unspec:DI [
(match_operand:DI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 4178))]
+ ] 4166))]
"CGEN_ENABLE_INSN_P (686)"
"cmov\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -25390,9 +25390,9 @@
(define_insn "cgen_intrinsic_cmov_crn_rm_p0"
[(set (match_operand:DI 0 "nonimmediate_operand" "=x")
- (unspec_volatile:DI [
+ (unspec:DI [
(match_operand:SI 1 "general_operand" "r")
- ] 3566))]
+ ] 4166))]
"CGEN_ENABLE_INSN_P (687)"
"cmov\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -25409,7 +25409,7 @@
(match_operand:SI 0 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3568)
+ ] 3556)
(const_int 0))
(match_dup 0)
(pc)))
@@ -25418,13 +25418,13 @@
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3570))
+ ] 3558))
(set (reg:SI 133)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3571))]
+ ] 3559))]
"CGEN_ENABLE_INSN_P (688)"
"bsrv\\t%l0"
[(set_attr "may_trap" "no")
@@ -25441,19 +25441,19 @@
(match_operand:SI 0 "general_operand" "r")
(reg:SI 32)
(reg:SI 42)
- ] 3572))
+ ] 3560))
(set (reg:SI 17)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3574))
+ ] 3562))
(set (reg:SI 133)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3575))]
+ ] 3563))]
"CGEN_ENABLE_INSN_P (689)"
"jsrv\\t%0"
[(set_attr "may_trap" "no")
@@ -25467,7 +25467,7 @@
(define_insn "cgen_intrinsic_synccp"
[(unspec_volatile [
(const_int 0)
- ] 3576)]
+ ] 3564)]
"CGEN_ENABLE_INSN_P (690)"
"synccp"
[(set_attr "may_trap" "no")
@@ -25486,7 +25486,7 @@
(reg:SI 32)
(reg:SI 42)
(reg:SI 81)
- ] 3578)
+ ] 3566)
(const_int 0))
(match_dup 1)
(pc)))]
@@ -25508,7 +25508,7 @@
(reg:SI 32)
(reg:SI 42)
(reg:SI 81)
- ] 3580)
+ ] 3568)
(const_int 0))
(match_dup 1)
(pc)))]
@@ -25530,7 +25530,7 @@
(reg:SI 32)
(reg:SI 42)
(reg:SI 81)
- ] 3582)
+ ] 3570)
(const_int 0))
(match_dup 1)
(pc)))]
@@ -25552,7 +25552,7 @@
(reg:SI 32)
(reg:SI 42)
(reg:SI 81)
- ] 3584)
+ ] 3572)
(const_int 0))
(match_dup 1)
(pc)))]
@@ -25573,14 +25573,14 @@
(match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 31)
(reg:SI 30)
- ] 3586))
+ ] 3574))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(match_dup 3)
(reg:SI 31)
(reg:SI 30)
- ] 3588))]
+ ] 3576))]
"CGEN_ENABLE_INSN_P (695)"
"lmcpm1\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25599,7 +25599,7 @@
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 31)
(reg:SI 30)
- ] 3590))]
+ ] 3578))]
"CGEN_ENABLE_INSN_P (696)"
"smcpm1\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25618,7 +25618,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 3592))
+ ] 3580))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -25626,7 +25626,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 3594))]
+ ] 3582))]
"CGEN_ENABLE_INSN_P (697)"
"lwcpm1\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25645,7 +25645,7 @@
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 31)
(reg:SI 30)
- ] 3596))
+ ] 3584))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
@@ -25653,7 +25653,7 @@
(match_dup 3)
(reg:SI 31)
(reg:SI 30)
- ] 3598))]
+ ] 3586))]
"CGEN_ENABLE_INSN_P (698)"
"swcpm1\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25672,7 +25672,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 3600))
+ ] 3588))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -25680,7 +25680,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 3602))]
+ ] 3590))]
"CGEN_ENABLE_INSN_P (699)"
"lhcpm1\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25699,7 +25699,7 @@
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 31)
(reg:SI 30)
- ] 3604))
+ ] 3592))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
@@ -25707,7 +25707,7 @@
(match_dup 3)
(reg:SI 31)
(reg:SI 30)
- ] 3606))]
+ ] 3594))]
"CGEN_ENABLE_INSN_P (700)"
"shcpm1\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25726,7 +25726,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 3608))
+ ] 3596))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -25734,7 +25734,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 3610))]
+ ] 3598))]
"CGEN_ENABLE_INSN_P (701)"
"lbcpm1\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25753,7 +25753,7 @@
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 31)
(reg:SI 30)
- ] 3612))
+ ] 3600))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
@@ -25761,7 +25761,7 @@
(match_dup 3)
(reg:SI 31)
(reg:SI 30)
- ] 3614))]
+ ] 3602))]
"CGEN_ENABLE_INSN_P (702)"
"sbcpm1\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25779,14 +25779,14 @@
(match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 29)
(reg:SI 28)
- ] 3616))
+ ] 3604))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(match_dup 3)
(reg:SI 29)
(reg:SI 28)
- ] 3618))]
+ ] 3606))]
"CGEN_ENABLE_INSN_P (703)"
"lmcpm0\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25805,7 +25805,7 @@
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 29)
(reg:SI 28)
- ] 3620))]
+ ] 3608))]
"CGEN_ENABLE_INSN_P (704)"
"smcpm0\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25824,7 +25824,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 3622))
+ ] 3610))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -25832,7 +25832,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 3624))]
+ ] 3612))]
"CGEN_ENABLE_INSN_P (705)"
"lwcpm0\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25851,7 +25851,7 @@
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 29)
(reg:SI 28)
- ] 3626))
+ ] 3614))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
@@ -25859,7 +25859,7 @@
(match_dup 3)
(reg:SI 29)
(reg:SI 28)
- ] 3628))]
+ ] 3616))]
"CGEN_ENABLE_INSN_P (706)"
"swcpm0\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25878,7 +25878,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 3630))
+ ] 3618))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -25886,7 +25886,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 3632))]
+ ] 3620))]
"CGEN_ENABLE_INSN_P (707)"
"lhcpm0\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25905,7 +25905,7 @@
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 29)
(reg:SI 28)
- ] 3634))
+ ] 3622))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
@@ -25913,7 +25913,7 @@
(match_dup 3)
(reg:SI 29)
(reg:SI 28)
- ] 3636))]
+ ] 3624))]
"CGEN_ENABLE_INSN_P (708)"
"shcpm0\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25932,7 +25932,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 3638))
+ ] 3626))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -25940,7 +25940,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 3640))]
+ ] 3628))]
"CGEN_ENABLE_INSN_P (709)"
"lbcpm0\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25959,7 +25959,7 @@
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(reg:SI 29)
(reg:SI 28)
- ] 3642))
+ ] 3630))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
@@ -25967,7 +25967,7 @@
(match_dup 3)
(reg:SI 29)
(reg:SI 28)
- ] 3644))]
+ ] 3632))]
"CGEN_ENABLE_INSN_P (710)"
"sbcpm0\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -25983,12 +25983,12 @@
(unspec:DI [
(match_operand:SI 2 "general_operand" "1")
(match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
- ] 3646))
+ ] 3634))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(match_dup 3)
- ] 3648))]
+ ] 3636))]
"CGEN_ENABLE_INSN_P (711)"
"lmcpa\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -26005,7 +26005,7 @@
(match_operand:DI 1 "general_operand" "em")
(match_operand:SI 2 "general_operand" "0")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
- ] 3650))]
+ ] 3638))]
"CGEN_ENABLE_INSN_P (712)"
"smcpa\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -26022,13 +26022,13 @@
(match_operand:SI 2 "general_operand" "1")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(mem:SI (scratch:SI))
- ] 3652))
+ ] 3640))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(match_dup 3)
(mem:SI (scratch:SI))
- ] 3654))]
+ ] 3642))]
"CGEN_ENABLE_INSN_P (713)"
"lwcpa\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -26045,13 +26045,13 @@
(match_operand:SI 1 "general_operand" "em")
(match_operand:SI 2 "general_operand" "0")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
- ] 3656))
+ ] 3644))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 3658))]
+ ] 3646))]
"CGEN_ENABLE_INSN_P (714)"
"swcpa\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -26068,13 +26068,13 @@
(match_operand:SI 2 "general_operand" "1")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(mem:SI (scratch:SI))
- ] 3660))
+ ] 3648))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(match_dup 3)
(mem:SI (scratch:SI))
- ] 3662))]
+ ] 3650))]
"CGEN_ENABLE_INSN_P (715)"
"lhcpa\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -26091,13 +26091,13 @@
(match_operand:SI 1 "general_operand" "em")
(match_operand:SI 2 "general_operand" "0")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
- ] 3664))
+ ] 3652))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 3666))]
+ ] 3654))]
"CGEN_ENABLE_INSN_P (716)"
"shcpa\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -26114,13 +26114,13 @@
(match_operand:SI 2 "general_operand" "1")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(mem:SI (scratch:SI))
- ] 3668))
+ ] 3656))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(match_dup 3)
(mem:SI (scratch:SI))
- ] 3670))]
+ ] 3658))]
"CGEN_ENABLE_INSN_P (717)"
"lbcpa\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -26137,13 +26137,13 @@
(match_operand:SI 1 "general_operand" "em")
(match_operand:SI 2 "general_operand" "0")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
- ] 3672))
+ ] 3660))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 3674))]
+ ] 3662))]
"CGEN_ENABLE_INSN_P (718)"
"sbcpa\\t%1,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -26159,7 +26159,7 @@
(unspec:DI [
(match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 3676))]
+ ] 3664))]
"CGEN_ENABLE_INSN_P (719)"
"lmcp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -26175,7 +26175,7 @@
(match_operand:DI 0 "general_operand" "em")
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 3678)]
+ ] 3666)]
"CGEN_ENABLE_INSN_P (720)"
"smcp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -26192,7 +26192,7 @@
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 3680))]
+ ] 3668))]
"CGEN_ENABLE_INSN_P (721)"
"lwcp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -26209,7 +26209,7 @@
(match_operand:SI 0 "general_operand" "em")
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 3682))]
+ ] 3670))]
"CGEN_ENABLE_INSN_P (722)"
"swcp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -26224,11 +26224,11 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=em")
(unspec:DI [
(match_operand:SI 2 "general_operand" "1")
- ] 3684))
+ ] 3672))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
- ] 3686))]
+ ] 3674))]
"CGEN_ENABLE_INSN_P (723)"
"lmcpi\\t%0,(%2+)"
[(set_attr "may_trap" "no")
@@ -26244,7 +26244,7 @@
(unspec:SI [
(match_operand:DI 1 "general_operand" "em")
(match_operand:SI 2 "general_operand" "0")
- ] 3688))]
+ ] 3676))]
"CGEN_ENABLE_INSN_P (724)"
"smcpi\\t%1,(%2+)"
[(set_attr "may_trap" "no")
@@ -26260,12 +26260,12 @@
(unspec:SI [
(match_operand:SI 2 "general_operand" "1")
(mem:SI (scratch:SI))
- ] 3690))
+ ] 3678))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(mem:SI (scratch:SI))
- ] 3692))]
+ ] 3680))]
"CGEN_ENABLE_INSN_P (725)"
"lwcpi\\t%0,(%2+)"
[(set_attr "may_trap" "no")
@@ -26281,12 +26281,12 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "em")
(match_operand:SI 2 "general_operand" "0")
- ] 3694))
+ ] 3682))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3696))]
+ ] 3684))]
"CGEN_ENABLE_INSN_P (726)"
"swcpi\\t%1,(%2+)"
[(set_attr "may_trap" "no")
@@ -26301,7 +26301,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=em")
(unspec:DI [
(match_operand:SI 1 "general_operand" "r")
- ] 3698))]
+ ] 3686))]
"CGEN_ENABLE_INSN_P (727)"
"lmcp\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -26316,7 +26316,7 @@
[(unspec_volatile [
(match_operand:DI 0 "general_operand" "em")
(match_operand:SI 1 "general_operand" "r")
- ] 3700)]
+ ] 3688)]
"CGEN_ENABLE_INSN_P (728)"
"smcp\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -26332,7 +26332,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 3702))]
+ ] 3690))]
"CGEN_ENABLE_INSN_P (729)"
"lwcp\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -26348,7 +26348,7 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "em")
(match_operand:SI 1 "general_operand" "r")
- ] 3704))]
+ ] 3692))]
"CGEN_ENABLE_INSN_P (730)"
"swcp\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -26364,7 +26364,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3706))]
+ ] 3694))]
"CGEN_ENABLE_INSN_P (731)"
"ssubu\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26380,7 +26380,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3708))]
+ ] 3696))]
"CGEN_ENABLE_INSN_P (732)"
"saddu\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26396,7 +26396,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3710))]
+ ] 3698))]
"CGEN_ENABLE_INSN_P (733)"
"ssub\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26412,7 +26412,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3712))]
+ ] 3700))]
"CGEN_ENABLE_INSN_P (734)"
"sadd\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26428,7 +26428,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
- ] 3714))]
+ ] 3702))]
"CGEN_ENABLE_INSN_P (735)"
"clipu\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26444,7 +26444,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
- ] 3716))]
+ ] 3704))]
"CGEN_ENABLE_INSN_P (736)"
"clip\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26460,7 +26460,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3718))]
+ ] 3706))]
"CGEN_ENABLE_INSN_P (737)"
"maxu\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26476,7 +26476,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3720))]
+ ] 3708))]
"CGEN_ENABLE_INSN_P (738)"
"minu\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26492,7 +26492,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3722))]
+ ] 3710))]
"CGEN_ENABLE_INSN_P (739)"
"max\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26508,7 +26508,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3724))]
+ ] 3712))]
"CGEN_ENABLE_INSN_P (740)"
"min\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26524,7 +26524,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3726))]
+ ] 3714))]
"CGEN_ENABLE_INSN_P (741)"
"ave\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26540,7 +26540,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3728))]
+ ] 3716))]
"CGEN_ENABLE_INSN_P (742)"
"abs\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26555,7 +26555,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
- ] 3730))]
+ ] 3718))]
"CGEN_ENABLE_INSN_P (743)"
"ldz\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -26570,7 +26570,7 @@
[(set (reg:SI 40)
(unspec_volatile:SI [
(reg:SI 40)
- ] 3732))]
+ ] 3720))]
"CGEN_ENABLE_INSN_P (744)"
"dbreak"
[(set_attr "may_trap" "yes")
@@ -26586,17 +26586,17 @@
(unspec:SI [
(reg:SI 41)
(reg:SI 40)
- ] 3734))
+ ] 3722))
(set (reg:SI 40)
(unspec:SI [
(reg:SI 41)
(reg:SI 40)
- ] 3736))
+ ] 3724))
(set (reg:SI 134)
(unspec:SI [
(reg:SI 41)
(reg:SI 40)
- ] 3737))]
+ ] 3725))]
"CGEN_ENABLE_INSN_P (745)"
"dret"
[(set_attr "may_trap" "no")
@@ -26612,27 +26612,27 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
- ] 3738))
+ ] 3726))
(set (reg:SI 24)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3740))
+ ] 3728))
(set (reg:SI 135)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3741))
+ ] 3729))
(set (reg:SI 23)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3742))
+ ] 3730))
(set (reg:SI 136)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3743))]
+ ] 3731))]
"CGEN_ENABLE_INSN_P (746)"
"divu\\t%0,%1"
[(set_attr "may_trap" "yes")
@@ -26648,27 +26648,27 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
- ] 3744))
+ ] 3732))
(set (reg:SI 24)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3746))
+ ] 3734))
(set (reg:SI 135)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3747))
+ ] 3735))
(set (reg:SI 23)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3748))
+ ] 3736))
(set (reg:SI 136)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3749))]
+ ] 3737))]
"CGEN_ENABLE_INSN_P (747)"
"div\\t%0,%1"
[(set_attr "may_trap" "yes")
@@ -26686,35 +26686,35 @@
(match_operand:SI 2 "general_operand" "r")
(reg:SI 24)
(reg:SI 23)
- ] 3750))
+ ] 3738))
(set (reg:SI 24)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
- ] 3752))
+ ] 3740))
(set (reg:SI 135)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
- ] 3753))
+ ] 3741))
(set (reg:SI 23)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
- ] 3754))
+ ] 3742))
(set (reg:SI 136)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
- ] 3755))]
+ ] 3743))]
"CGEN_ENABLE_INSN_P (748)"
"maddru\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26732,35 +26732,35 @@
(match_operand:SI 2 "general_operand" "r")
(reg:SI 24)
(reg:SI 23)
- ] 3756))
+ ] 3744))
(set (reg:SI 24)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
- ] 3758))
+ ] 3746))
(set (reg:SI 135)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
- ] 3759))
+ ] 3747))
(set (reg:SI 23)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
- ] 3760))
+ ] 3748))
(set (reg:SI 136)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
- ] 3761))]
+ ] 3749))]
"CGEN_ENABLE_INSN_P (749)"
"maddr\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26778,28 +26778,28 @@
(match_operand:SI 1 "general_operand" "r")
(reg:SI 24)
(reg:SI 23)
- ] 3762))
+ ] 3750))
(set (reg:SI 135)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
- ] 3763))
+ ] 3751))
(set (reg:SI 23)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
- ] 3764))
+ ] 3752))
(set (reg:SI 136)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
- ] 3765))]
+ ] 3753))]
"CGEN_ENABLE_INSN_P (750)"
"maddu\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -26817,28 +26817,28 @@
(match_operand:SI 1 "general_operand" "r")
(reg:SI 24)
(reg:SI 23)
- ] 3766))
+ ] 3754))
(set (reg:SI 135)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
- ] 3767))
+ ] 3755))
(set (reg:SI 23)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
- ] 3768))
+ ] 3756))
(set (reg:SI 136)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
- ] 3769))]
+ ] 3757))]
"CGEN_ENABLE_INSN_P (751)"
"madd\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -26854,27 +26854,27 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3770))
+ ] 3758))
(set (reg:SI 24)
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3772))
+ ] 3760))
(set (reg:SI 135)
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3773))
+ ] 3761))
(set (reg:SI 23)
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3774))
+ ] 3762))
(set (reg:SI 136)
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3775))]
+ ] 3763))]
"CGEN_ENABLE_INSN_P (752)"
"mulru\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26890,27 +26890,27 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3776))
+ ] 3764))
(set (reg:SI 24)
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3778))
+ ] 3766))
(set (reg:SI 135)
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3779))
+ ] 3767))
(set (reg:SI 23)
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3780))
+ ] 3768))
(set (reg:SI 136)
(unspec:SI [
(match_dup 1)
(match_dup 2)
- ] 3781))]
+ ] 3769))]
"CGEN_ENABLE_INSN_P (753)"
"mulr\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -26926,22 +26926,22 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
- ] 3782))
+ ] 3770))
(set (reg:SI 135)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3783))
+ ] 3771))
(set (reg:SI 23)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3784))
+ ] 3772))
(set (reg:SI 136)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3785))]
+ ] 3773))]
"CGEN_ENABLE_INSN_P (754)"
"mulu\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -26957,22 +26957,22 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
- ] 3786))
+ ] 3774))
(set (reg:SI 135)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3787))
+ ] 3775))
(set (reg:SI 23)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3788))
+ ] 3776))
(set (reg:SI 136)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3789))]
+ ] 3777))]
"CGEN_ENABLE_INSN_P (755)"
"mul\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -26987,7 +26987,7 @@
[(unspec_volatile [
(match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
(match_operand:SI 1 "general_operand" "r")
- ] 3790)]
+ ] 3778)]
"CGEN_ENABLE_INSN_P (756)"
"cache\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -27003,12 +27003,12 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 3792))
+ ] 3780))
(set (mem:SI (scratch:SI))
(unspec:SI [
(match_dup 1)
(mem:SI (scratch:SI))
- ] 3794))]
+ ] 3782))]
"CGEN_ENABLE_INSN_P (757)"
"tas\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -27025,7 +27025,7 @@
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(mem:SI (scratch:SI))
- ] 3796))]
+ ] 3784))]
"CGEN_ENABLE_INSN_P (758)"
"btstm\\t$0,(%1),%2"
[(set_attr "may_trap" "no")
@@ -27042,7 +27042,7 @@
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
(mem:SI (scratch:SI))
- ] 3798))]
+ ] 3786))]
"CGEN_ENABLE_INSN_P (759)"
"bnotm\\t(%0),%1"
[(set_attr "may_trap" "no")
@@ -27059,7 +27059,7 @@
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
(mem:SI (scratch:SI))
- ] 3800))]
+ ] 3788))]
"CGEN_ENABLE_INSN_P (760)"
"bclrm\\t(%0),%1"
[(set_attr "may_trap" "no")
@@ -27076,7 +27076,7 @@
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
(mem:SI (scratch:SI))
- ] 3802))]
+ ] 3790))]
"CGEN_ENABLE_INSN_P (761)"
"bsetm\\t(%0),%1"
[(set_attr "may_trap" "no")
@@ -27091,7 +27091,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec_volatile:SI [
(match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
- ] 3804))]
+ ] 3792))]
"CGEN_ENABLE_INSN_P (762)"
"ldcb\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -27106,7 +27106,7 @@
[(unspec_volatile [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
- ] 3806)]
+ ] 3794)]
"CGEN_ENABLE_INSN_P (763)"
"stcb\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -27120,7 +27120,7 @@
(define_insn "cgen_intrinsic_syncm"
[(unspec_volatile [
(const_int 0)
- ] 3808)]
+ ] 3796)]
"CGEN_ENABLE_INSN_P (764)"
"syncm"
[(set_attr "may_trap" "no")
@@ -27135,7 +27135,7 @@
[(set (pc)
(unspec_volatile:SI [
(const_int 0)
- ] 3810))]
+ ] 3798))]
"CGEN_ENABLE_INSN_P (765)"
"break"
[(set_attr "may_trap" "yes")
@@ -27151,7 +27151,7 @@
(unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_2a1_immediate" "")
(reg:SI 36)
- ] 3812))]
+ ] 3800))]
"CGEN_ENABLE_INSN_P (766)"
"swi\\t%0"
[(set_attr "may_trap" "yes")
@@ -27165,7 +27165,7 @@
(define_insn "cgen_intrinsic_sleep"
[(unspec_volatile [
(const_int 0)
- ] 3814)]
+ ] 3802)]
"CGEN_ENABLE_INSN_P (767)"
"sleep"
[(set_attr "may_trap" "no")
@@ -27179,7 +27179,7 @@
(define_insn "cgen_intrinsic_halt"
[(unspec_volatile [
(reg:SI 32)
- ] 3816)]
+ ] 3804)]
"CGEN_ENABLE_INSN_P (768)"
"halt"
[(set_attr "may_trap" "no")
@@ -27197,7 +27197,7 @@
(reg:SI 42)
(reg:SI 39)
(reg:SI 35)
- ] 3818))]
+ ] 3806))]
"CGEN_ENABLE_INSN_P (769)"
"reti"
[(set_attr "may_trap" "no")
@@ -27212,7 +27212,7 @@
[(set (reg:SI 32)
(unspec_volatile:SI [
(reg:SI 32)
- ] 3820))]
+ ] 3808))]
"CGEN_ENABLE_INSN_P (770)"
"ei"
[(set_attr "may_trap" "no")
@@ -27227,7 +27227,7 @@
[(set (reg:SI 32)
(unspec_volatile:SI [
(reg:SI 32)
- ] 3822))]
+ ] 3810))]
"CGEN_ENABLE_INSN_P (771)"
"di"
[(set_attr "may_trap" "no")
@@ -27244,7 +27244,7 @@
(match_operand:SI 1 "general_operand" "c")
(reg:SI 32)
(reg:SI 42)
- ] 3824))]
+ ] 3812))]
"CGEN_ENABLE_INSN_P (772)"
"ldc\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -27259,7 +27259,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(reg:SI 24)
- ] 3826))]
+ ] 3814))]
"CGEN_ENABLE_INSN_P (773)"
"ldc\\t%0,$lo"
[(set_attr "may_trap" "no")
@@ -27274,7 +27274,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(reg:SI 23)
- ] 3828))]
+ ] 3816))]
"CGEN_ENABLE_INSN_P (774)"
"ldc\\t%0,$hi"
[(set_attr "may_trap" "no")
@@ -27289,7 +27289,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(reg:SI 17)
- ] 3830))]
+ ] 3818))]
"CGEN_ENABLE_INSN_P (775)"
"ldc\\t%0,$lp"
[(set_attr "may_trap" "no")
@@ -27304,7 +27304,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=c")
(unspec_volatile:SI [
(match_operand:SI 1 "general_operand" "r")
- ] 3832))]
+ ] 3820))]
"CGEN_ENABLE_INSN_P (776)"
"stc\\t%1,%0"
[(set_attr "may_trap" "no")
@@ -27319,11 +27319,11 @@
[(set (reg:SI 24)
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
- ] 3834))
+ ] 3822))
(set (reg:SI 135)
(unspec:SI [
(match_dup 0)
- ] 3835))]
+ ] 3823))]
"CGEN_ENABLE_INSN_P (777)"
"stc\\t%0,$lo"
[(set_attr "may_trap" "no")
@@ -27338,11 +27338,11 @@
[(set (reg:SI 23)
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
- ] 3836))
+ ] 3824))
(set (reg:SI 136)
(unspec:SI [
(match_dup 0)
- ] 3837))]
+ ] 3825))]
"CGEN_ENABLE_INSN_P (778)"
"stc\\t%0,$hi"
[(set_attr "may_trap" "no")
@@ -27357,11 +27357,11 @@
[(set (reg:SI 17)
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
- ] 3838))
+ ] 3826))
(set (reg:SI 133)
(unspec:SI [
(match_dup 0)
- ] 3839))]
+ ] 3827))]
"CGEN_ENABLE_INSN_P (779)"
"stc\\t%0,$lp"
[(set_attr "may_trap" "no")
@@ -27378,37 +27378,37 @@
(match_operand:SI 0 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3840))
+ ] 3828))
(set (reg:SI 137)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3841))
+ ] 3829))
(set (reg:SI 21)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3842))
+ ] 3830))
(set (reg:SI 138)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3843))
+ ] 3831))
(set (reg:SI 20)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3844))
+ ] 3832))
(set (reg:SI 139)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3845))]
+ ] 3833))]
"CGEN_ENABLE_INSN_P (780)"
"erepeat\\t%l0"
[(set_attr "may_trap" "no")
@@ -27426,42 +27426,42 @@
(match_operand:SI 1 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3846))
+ ] 3834))
(set (reg:SI 137)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 32)
(reg:SI 42)
- ] 3847))
+ ] 3835))
(set (reg:SI 21)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 32)
(reg:SI 42)
- ] 3848))
+ ] 3836))
(set (reg:SI 138)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 32)
(reg:SI 42)
- ] 3849))
+ ] 3837))
(set (reg:SI 20)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 32)
(reg:SI 42)
- ] 3850))
+ ] 3838))
(set (reg:SI 139)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 32)
(reg:SI 42)
- ] 3851))]
+ ] 3839))]
"CGEN_ENABLE_INSN_P (781)"
"repeat\\t%0,%l1"
[(set_attr "may_trap" "no")
@@ -27478,7 +27478,7 @@
(reg:SI 32)
(reg:SI 42)
(reg:SI 17)
- ] 3852))]
+ ] 3840))]
"CGEN_ENABLE_INSN_P (782)"
"ret"
[(set_attr "may_trap" "no")
@@ -27495,19 +27495,19 @@
(match_operand:SI 0 "general_operand" "r")
(reg:SI 32)
(reg:SI 42)
- ] 3854))
+ ] 3842))
(set (reg:SI 17)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3856))
+ ] 3844))
(set (reg:SI 133)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3857))]
+ ] 3845))]
"CGEN_ENABLE_INSN_P (783)"
"jsr\\t%0"
[(set_attr "may_trap" "no")
@@ -27524,7 +27524,7 @@
(match_operand:SI 0 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3858)
+ ] 3846)
(const_int 0))
(match_dup 0)
(pc)))]
@@ -27544,7 +27544,7 @@
(match_operand:SI 0 "general_operand" "r")
(reg:SI 32)
(reg:SI 42)
- ] 3860))]
+ ] 3848))]
"CGEN_ENABLE_INSN_P (785)"
"jmp\\t%0"
[(set_attr "may_trap" "no")
@@ -27561,7 +27561,7 @@
(match_operand:SI 0 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3866)
+ ] 3854)
(const_int 0))
(match_dup 0)
(pc)))
@@ -27570,13 +27570,13 @@
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3868))
+ ] 3856))
(set (reg:SI 133)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3869))]
+ ] 3857))]
"CGEN_ENABLE_INSN_P (786)"
"bsr\\t%l0"
[(set_attr "may_trap" "no")
@@ -27593,7 +27593,7 @@
(match_operand:SI 0 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3862)
+ ] 3850)
(const_int 0))
(match_dup 0)
(pc)))
@@ -27602,13 +27602,13 @@
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3864))
+ ] 3852))
(set (reg:SI 133)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 42)
- ] 3865))]
+ ] 3853))]
"CGEN_ENABLE_INSN_P (787)"
"bsr\\t%l0"
[(set_attr "may_trap" "no")
@@ -27627,7 +27627,7 @@
(match_operand:SI 2 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3870)
+ ] 3858)
(const_int 0))
(match_dup 2)
(pc)))]
@@ -27649,7 +27649,7 @@
(match_operand:SI 2 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3872)
+ ] 3860)
(const_int 0))
(match_dup 2)
(pc)))]
@@ -27671,7 +27671,7 @@
(match_operand:SI 2 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3874)
+ ] 3862)
(const_int 0))
(match_dup 2)
(pc)))]
@@ -27693,7 +27693,7 @@
(match_operand:SI 2 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3876)
+ ] 3864)
(const_int 0))
(match_dup 2)
(pc)))]
@@ -27715,7 +27715,7 @@
(match_operand:SI 2 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3878)
+ ] 3866)
(const_int 0))
(match_dup 2)
(pc)))]
@@ -27737,7 +27737,7 @@
(match_operand:SI 2 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3880)
+ ] 3868)
(const_int 0))
(match_dup 2)
(pc)))]
@@ -27758,7 +27758,7 @@
(match_operand:SI 1 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3882)
+ ] 3870)
(const_int 0))
(match_dup 1)
(pc)))]
@@ -27779,7 +27779,7 @@
(match_operand:SI 1 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3884)
+ ] 3872)
(const_int 0))
(match_dup 1)
(pc)))]
@@ -27799,7 +27799,7 @@
(match_operand:SI 0 "immediate_operand" "")
(reg:SI 32)
(reg:SI 42)
- ] 3886)
+ ] 3874)
(const_int 0))
(match_dup 0)
(pc)))]
@@ -27819,7 +27819,7 @@
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
(reg:SI 18)
- ] 3888))]
+ ] 3876))]
"CGEN_ENABLE_INSN_P (797)"
"fsft\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -27835,7 +27835,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
- ] 3890))]
+ ] 3878))]
"CGEN_ENABLE_INSN_P (798)"
"sll3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -27851,7 +27851,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
- ] 3892))]
+ ] 3880))]
"CGEN_ENABLE_INSN_P (799)"
"sll\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -27867,7 +27867,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
- ] 3894))]
+ ] 3882))]
"CGEN_ENABLE_INSN_P (800)"
"srl\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -27883,7 +27883,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
- ] 3896))]
+ ] 3884))]
"CGEN_ENABLE_INSN_P (801)"
"sra\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -27899,7 +27899,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3898))]
+ ] 3886))]
"CGEN_ENABLE_INSN_P (802)"
"sll\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -27915,7 +27915,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3900))]
+ ] 3888))]
"CGEN_ENABLE_INSN_P (803)"
"srl\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -27931,7 +27931,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3902))]
+ ] 3890))]
"CGEN_ENABLE_INSN_P (804)"
"sra\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -27947,7 +27947,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
- ] 3904))]
+ ] 3892))]
"CGEN_ENABLE_INSN_P (805)"
"xor3\\t%0,%1,%2"
[(set_attr "may_trap" "no")
@@ -27963,7 +27963,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
- ] 3906))]
+ ] 3894))]
"CGEN_ENABLE_INSN_P (806)"
"and3\\t%0,%1,%2"
[(set_attr "may_trap" "no")
@@ -27979,7 +27979,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
- ] 3908))]
+ ] 3896))]
"CGEN_ENABLE_INSN_P (807)"
"or3\\t%0,%1,%2"
[(set_attr "may_trap" "no")
@@ -27995,7 +27995,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3910))]
+ ] 3898))]
"CGEN_ENABLE_INSN_P (808)"
"nor\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -28011,7 +28011,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3912))]
+ ] 3900))]
"CGEN_ENABLE_INSN_P (809)"
"xor\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -28027,7 +28027,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3914))]
+ ] 3902))]
"CGEN_ENABLE_INSN_P (810)"
"and\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -28043,7 +28043,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3916))]
+ ] 3904))]
"CGEN_ENABLE_INSN_P (811)"
"or\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -28059,7 +28059,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
- ] 3918))]
+ ] 3906))]
"CGEN_ENABLE_INSN_P (812)"
"sltu3\\t%0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28075,7 +28075,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_sint_16a1_immediate" "")
- ] 3920))]
+ ] 3908))]
"CGEN_ENABLE_INSN_P (813)"
"slt3\\t%0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28091,7 +28091,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_sint_16a1_immediate" "")
- ] 3922))]
+ ] 3910))]
"CGEN_ENABLE_INSN_P (814)"
"add3\\t%0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28107,7 +28107,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "general_operand" "r")
- ] 3924))]
+ ] 3912))]
"CGEN_ENABLE_INSN_P (815)"
"sl2ad3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28123,7 +28123,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "general_operand" "r")
- ] 3926))]
+ ] 3914))]
"CGEN_ENABLE_INSN_P (816)"
"sl1ad3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28139,7 +28139,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
- ] 3928))]
+ ] 3916))]
"CGEN_ENABLE_INSN_P (817)"
"sltu3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28155,7 +28155,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
- ] 3930))]
+ ] 3918))]
"CGEN_ENABLE_INSN_P (818)"
"slt3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28171,7 +28171,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "general_operand" "r")
- ] 3932))]
+ ] 3920))]
"CGEN_ENABLE_INSN_P (819)"
"sltu3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28187,7 +28187,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "general_operand" "r")
- ] 3934))]
+ ] 3922))]
"CGEN_ENABLE_INSN_P (820)"
"slt3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28202,7 +28202,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
- ] 3936))]
+ ] 3924))]
"CGEN_ENABLE_INSN_P (821)"
"neg\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -28218,7 +28218,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "general_operand" "r")
- ] 3938))]
+ ] 3926))]
"CGEN_ENABLE_INSN_P (822)"
"sbvck3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28234,7 +28234,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
- ] 3940))]
+ ] 3928))]
"CGEN_ENABLE_INSN_P (823)"
"sub\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -28250,7 +28250,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "general_operand" "r")
- ] 3942))]
+ ] 3930))]
"CGEN_ENABLE_INSN_P (824)"
"advck3\\t$0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28266,7 +28266,7 @@
(unspec:SI [
(match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
(reg:SI 15)
- ] 3944))]
+ ] 3932))]
"CGEN_ENABLE_INSN_P (825)"
"add3\\t%0,$sp,%1"
[(set_attr "may_trap" "no")
@@ -28282,7 +28282,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "cgen_h_sint_6a1_immediate" "")
- ] 3946))]
+ ] 3934))]
"CGEN_ENABLE_INSN_P (826)"
"add\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -28298,7 +28298,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(match_operand:SI 2 "general_operand" "r")
- ] 3948))]
+ ] 3936))]
"CGEN_ENABLE_INSN_P (827)"
"add3\\t%0,%1,%2"
[(set_attr "may_trap" "no")
@@ -28313,7 +28313,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
- ] 3950))]
+ ] 3938))]
"CGEN_ENABLE_INSN_P (828)"
"movh\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -28328,7 +28328,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
- ] 3952))]
+ ] 3940))]
"CGEN_ENABLE_INSN_P (829)"
"movu\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -28343,7 +28343,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=t")
(unspec:SI [
(match_operand:SI 1 "cgen_h_uint_24a1_immediate" "")
- ] 3954))]
+ ] 3942))]
"CGEN_ENABLE_INSN_P (830)"
"movu\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -28358,7 +28358,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "cgen_h_sint_8a1_immediate" "")
- ] 3958))]
+ ] 3946))]
"CGEN_ENABLE_INSN_P (831)"
"mov\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -28373,7 +28373,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
- ] 3956))]
+ ] 3944))]
"CGEN_ENABLE_INSN_P (832)"
"mov\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -28388,7 +28388,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
- ] 3960))]
+ ] 3948))]
"CGEN_ENABLE_INSN_P (833)"
"mov\\t%0,%1"
[(set_attr "may_trap" "no")
@@ -28404,12 +28404,12 @@
(unspec:SI [
(match_operand:SI 0 "cgen_h_sint_2a1_immediate" "")
(match_operand:SI 1 "general_operand" "r")
- ] 3962))
+ ] 3950))
(set (reg:SI 140)
(unspec:SI [
(match_dup 0)
(match_dup 1)
- ] 3963))]
+ ] 3951))]
"CGEN_ENABLE_INSN_P (834)"
"ssarb\\t%0(%1)"
[(set_attr "may_trap" "no")
@@ -28424,7 +28424,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
- ] 3964))]
+ ] 3952))]
"CGEN_ENABLE_INSN_P (835)"
"extuh\\t%1"
[(set_attr "may_trap" "no")
@@ -28439,7 +28439,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
- ] 3966))]
+ ] 3954))]
"CGEN_ENABLE_INSN_P (836)"
"extub\\t%1"
[(set_attr "may_trap" "no")
@@ -28454,7 +28454,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
- ] 3968))]
+ ] 3956))]
"CGEN_ENABLE_INSN_P (837)"
"exth\\t%1"
[(set_attr "may_trap" "no")
@@ -28469,7 +28469,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec:SI [
(match_operand:SI 1 "general_operand" "0")
- ] 3970))]
+ ] 3958))]
"CGEN_ENABLE_INSN_P (838)"
"extb\\t%1"
[(set_attr "may_trap" "no")
@@ -28485,7 +28485,7 @@
(unspec:SI [
(match_operand:SI 1 "cgen_h_uint_22a4_immediate" "")
(mem:SI (scratch:SI))
- ] 3972))]
+ ] 3960))]
"CGEN_ENABLE_INSN_P (839)"
"lw\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28501,7 +28501,7 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_uint_22a4_immediate" "")
- ] 3974))]
+ ] 3962))]
"CGEN_ENABLE_INSN_P (840)"
"sw\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28518,7 +28518,7 @@
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 3976))]
+ ] 3964))]
"CGEN_ENABLE_INSN_P (841)"
"lhu\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -28535,7 +28535,7 @@
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 3978))]
+ ] 3966))]
"CGEN_ENABLE_INSN_P (842)"
"lbu\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -28552,7 +28552,7 @@
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 3980))]
+ ] 3968))]
"CGEN_ENABLE_INSN_P (843)"
"lw\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -28569,7 +28569,7 @@
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 3982))]
+ ] 3970))]
"CGEN_ENABLE_INSN_P (844)"
"lh\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -28586,7 +28586,7 @@
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 3984))]
+ ] 3972))]
"CGEN_ENABLE_INSN_P (845)"
"lb\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -28603,7 +28603,7 @@
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 3986))]
+ ] 3974))]
"CGEN_ENABLE_INSN_P (846)"
"sw\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -28620,7 +28620,7 @@
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 3988))]
+ ] 3976))]
"CGEN_ENABLE_INSN_P (847)"
"sh\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -28637,7 +28637,7 @@
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 3990))]
+ ] 3978))]
"CGEN_ENABLE_INSN_P (848)"
"sb\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -28654,7 +28654,7 @@
(match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
(reg:SI 13)
(mem:SI (scratch:SI))
- ] 3992))]
+ ] 3980))]
"CGEN_ENABLE_INSN_P (849)"
"lhu\\t%0,%1($tp)"
[(set_attr "may_trap" "no")
@@ -28671,7 +28671,7 @@
(match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
(reg:SI 13)
(mem:SI (scratch:SI))
- ] 3994))]
+ ] 3982))]
"CGEN_ENABLE_INSN_P (850)"
"lbu\\t%0,%1($tp)"
[(set_attr "may_trap" "no")
@@ -28688,7 +28688,7 @@
(match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
(reg:SI 13)
(mem:SI (scratch:SI))
- ] 3996))]
+ ] 3984))]
"CGEN_ENABLE_INSN_P (851)"
"lw\\t%0,%1($tp)"
[(set_attr "may_trap" "no")
@@ -28705,7 +28705,7 @@
(match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
(reg:SI 13)
(mem:SI (scratch:SI))
- ] 3998))]
+ ] 3986))]
"CGEN_ENABLE_INSN_P (852)"
"lh\\t%0,%1($tp)"
[(set_attr "may_trap" "no")
@@ -28722,7 +28722,7 @@
(match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
(reg:SI 13)
(mem:SI (scratch:SI))
- ] 4000))]
+ ] 3988))]
"CGEN_ENABLE_INSN_P (853)"
"lb\\t%0,%1($tp)"
[(set_attr "may_trap" "no")
@@ -28739,7 +28739,7 @@
(match_operand:SI 0 "general_operand" "t")
(match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
(reg:SI 13)
- ] 4002))]
+ ] 3990))]
"CGEN_ENABLE_INSN_P (854)"
"sw\\t%0,%1($tp)"
[(set_attr "may_trap" "no")
@@ -28756,7 +28756,7 @@
(match_operand:SI 0 "general_operand" "t")
(match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
(reg:SI 13)
- ] 4004))]
+ ] 3992))]
"CGEN_ENABLE_INSN_P (855)"
"sh\\t%0,%1($tp)"
[(set_attr "may_trap" "no")
@@ -28773,7 +28773,7 @@
(match_operand:SI 0 "general_operand" "t")
(match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
(reg:SI 13)
- ] 4006))]
+ ] 3994))]
"CGEN_ENABLE_INSN_P (856)"
"sb\\t%0,%1($tp)"
[(set_attr "may_trap" "no")
@@ -28790,7 +28790,7 @@
(match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
(reg:SI 15)
(mem:SI (scratch:SI))
- ] 4008))]
+ ] 3996))]
"CGEN_ENABLE_INSN_P (857)"
"lw\\t%0,%1($sp)"
[(set_attr "may_trap" "no")
@@ -28807,7 +28807,7 @@
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
(reg:SI 15)
- ] 4010))]
+ ] 3998))]
"CGEN_ENABLE_INSN_P (858)"
"sw\\t%0,%1($sp)"
[(set_attr "may_trap" "no")
@@ -28823,7 +28823,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4012))]
+ ] 4000))]
"CGEN_ENABLE_INSN_P (859)"
"lhu\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28839,7 +28839,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4014))]
+ ] 4002))]
"CGEN_ENABLE_INSN_P (860)"
"lbu\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28855,7 +28855,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4016))]
+ ] 4004))]
"CGEN_ENABLE_INSN_P (861)"
"lw\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28871,7 +28871,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4018))]
+ ] 4006))]
"CGEN_ENABLE_INSN_P (862)"
"lh\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28887,7 +28887,7 @@
(unspec:SI [
(match_operand:SI 1 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4020))]
+ ] 4008))]
"CGEN_ENABLE_INSN_P (863)"
"lb\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28903,7 +28903,7 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
- ] 4022))]
+ ] 4010))]
"CGEN_ENABLE_INSN_P (864)"
"sw\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28919,7 +28919,7 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
- ] 4024))]
+ ] 4012))]
"CGEN_ENABLE_INSN_P (865)"
"sh\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28935,7 +28935,7 @@
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
- ] 4026))]
+ ] 4014))]
"CGEN_ENABLE_INSN_P (866)"
"sb\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -28951,7 +28951,7 @@
(unspec_volatile:SI [
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "cgen_h_uint_20a1_immediate" "")
- ] 4028))]
+ ] 4016))]
"CGEN_ENABLE_INSN_P (867)"
"dsp1\\t%1,%2"
[(set_attr "may_trap" "no")
@@ -28965,7 +28965,7 @@
(define_insn "cgen_intrinsic_dsp0"
[(unspec_volatile [
(match_operand:SI 0 "cgen_h_uint_24a1_immediate" "")
- ] 4030)]
+ ] 4018)]
"CGEN_ENABLE_INSN_P (868)"
"dsp0\\t%0"
[(set_attr "may_trap" "no")
@@ -28982,7 +28982,7 @@
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
(match_operand:SI 3 "cgen_h_uint_16a1_immediate" "")
- ] 4032))]
+ ] 4020))]
"CGEN_ENABLE_INSN_P (869)"
"dsp\\t%1,%2,%3"
[(set_attr "may_trap" "no")
@@ -28999,7 +28999,7 @@
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
(match_operand:SI 3 "cgen_h_uint_16a1_immediate" "")
- ] 4034))]
+ ] 4022))]
"CGEN_ENABLE_INSN_P (870)"
"uci\\t%1,%2,%3"
[(set_attr "may_trap" "no")
@@ -29018,7 +29018,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 4036))
+ ] 4024))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -29026,7 +29026,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 4038))]
+ ] 4026))]
"CGEN_ENABLE_INSN_P (871)"
"lhucpm1\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -29045,7 +29045,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 4040))
+ ] 4028))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -29053,7 +29053,7 @@
(reg:SI 31)
(reg:SI 30)
(mem:SI (scratch:SI))
- ] 4042))]
+ ] 4030))]
"CGEN_ENABLE_INSN_P (872)"
"lbucpm1\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -29072,7 +29072,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 4044))
+ ] 4032))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -29080,7 +29080,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 4046))]
+ ] 4034))]
"CGEN_ENABLE_INSN_P (873)"
"lhucpm0\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -29099,7 +29099,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 4048))
+ ] 4036))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
@@ -29107,7 +29107,7 @@
(reg:SI 29)
(reg:SI 28)
(mem:SI (scratch:SI))
- ] 4050))]
+ ] 4038))]
"CGEN_ENABLE_INSN_P (874)"
"lbucpm0\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -29124,13 +29124,13 @@
(match_operand:SI 2 "general_operand" "1")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(mem:SI (scratch:SI))
- ] 4052))
+ ] 4040))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(match_dup 3)
(mem:SI (scratch:SI))
- ] 4054))]
+ ] 4042))]
"CGEN_ENABLE_INSN_P (875)"
"lhucpa\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -29147,13 +29147,13 @@
(match_operand:SI 2 "general_operand" "1")
(match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
(mem:SI (scratch:SI))
- ] 4056))
+ ] 4044))
(set (match_operand:SI 1 "nonimmediate_operand" "=r")
(unspec:SI [
(match_dup 2)
(match_dup 3)
(mem:SI (scratch:SI))
- ] 4058))]
+ ] 4046))]
"CGEN_ENABLE_INSN_P (876)"
"lbucpa\\t%0,(%2+),%3"
[(set_attr "may_trap" "no")
@@ -29170,7 +29170,7 @@
(match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4060))]
+ ] 4048))]
"CGEN_ENABLE_INSN_P (877)"
"lhucp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -29187,7 +29187,7 @@
(match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4062))]
+ ] 4050))]
"CGEN_ENABLE_INSN_P (878)"
"lhcp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -29204,7 +29204,7 @@
(match_operand:SI 0 "general_operand" "em")
(match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 4064))]
+ ] 4052))]
"CGEN_ENABLE_INSN_P (879)"
"shcp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -29221,7 +29221,7 @@
(match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4066))]
+ ] 4054))]
"CGEN_ENABLE_INSN_P (880)"
"lbucp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -29238,7 +29238,7 @@
(match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
(mem:SI (scratch:SI))
- ] 4068))]
+ ] 4056))]
"CGEN_ENABLE_INSN_P (881)"
"lbcp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -29255,7 +29255,7 @@
(match_operand:SI 0 "general_operand" "em")
(match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 4070))]
+ ] 4058))]
"CGEN_ENABLE_INSN_P (882)"
"sbcp\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -29272,7 +29272,7 @@
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
(match_operand:SI 3 "general_operand" "r")
- ] 4072))]
+ ] 4060))]
"CGEN_ENABLE_INSN_P (883)"
"casw3\\t%1,%2,(%3)"
[(set_attr "may_trap" "no")
@@ -29289,7 +29289,7 @@
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
(match_operand:SI 3 "general_operand" "r")
- ] 4074))]
+ ] 4062))]
"CGEN_ENABLE_INSN_P (884)"
"cash3\\t%1,%2,(%3)"
[(set_attr "may_trap" "no")
@@ -29306,7 +29306,7 @@
(match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "r")
(match_operand:SI 3 "general_operand" "r")
- ] 4076))]
+ ] 4064))]
"CGEN_ENABLE_INSN_P (885)"
"casb3\\t%1,%2,(%3)"
[(set_attr "may_trap" "no")
@@ -29322,7 +29322,7 @@
(match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
(match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
(match_operand:SI 2 "general_operand" "r")
- ] 4078)]
+ ] 4066)]
"CGEN_ENABLE_INSN_P (886)"
"pref\\t%0,%1(%2)"
[(set_attr "may_trap" "no")
@@ -29337,7 +29337,7 @@
[(unspec_volatile [
(match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
(match_operand:SI 1 "general_operand" "r")
- ] 4080)]
+ ] 4068)]
"CGEN_ENABLE_INSN_P (887)"
"pref\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -29352,7 +29352,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(unspec_volatile:SI [
(match_operand:SI 1 "general_operand" "r")
- ] 4082))]
+ ] 4070))]
"CGEN_ENABLE_INSN_P (888)"
"ldcb\\t%0,(%1)"
[(set_attr "may_trap" "no")
@@ -29367,7 +29367,7 @@
[(unspec_volatile [
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
- ] 4084)]
+ ] 4072)]
"CGEN_ENABLE_INSN_P (889)"
"stcb\\t%0,(%1)"
[(set_attr "may_trap" "no")
diff --git a/gcc/config/mep/mep-intrin.h b/gcc/config/mep/mep-intrin.h
index 8af4cb1..74f330d 100644
--- a/gcc/config/mep/mep-intrin.h
+++ b/gcc/config/mep/mep-intrin.h
@@ -18,75 +18,75 @@
#ifndef __MEP__
enum {
- mep_fcmpleis = 597,
- mep_fcmplis = 599,
- mep_fcmpes = 601,
- mep_fcmpules = 603,
- mep_fcmpuls = 605,
- mep_fcmpues = 607,
- mep_fcmpus = 609,
- mep_fcvtsw = 611,
- mep_ftruncws = 613,
- mep_fnegs = 615,
- mep_fabss = 617,
- mep_fsqrts = 619,
- mep_fdivs = 621,
- mep_fmuls = 623,
- mep_fsubs = 625,
- mep_fadds = 627,
- mep_fmovs = 629,
- mep_cextb = 630,
- mep_cexth = 631,
- mep_cextub = 632,
- mep_cextuh = 633,
- mep_xmula0 = 634,
- mep_cmula0 = 635,
- mep_cneg = 636,
- mep_cmovh2 = 638,
- mep_cmovh1 = 639,
- mep_cmovc2 = 640,
- mep_cmovc1 = 641,
- mep_cmov2 = 642,
- mep_cmov1 = 643,
- mep_cmovi = 644,
- mep_cpmov = 646,
- mep_cmov = 647,
- mep_csrai3 = 648,
- mep_csrai = 650,
- mep_csra3 = 652,
- mep_csra = 654,
- mep_csrli3 = 656,
- mep_csrli = 658,
- mep_csrl3 = 660,
- mep_csrl = 662,
- mep_cslli3 = 664,
- mep_cslli = 666,
- mep_csll3 = 668,
- mep_csll = 670,
- mep_cxori3 = 672,
- mep_cxori = 674,
- mep_cxor3 = 676,
- mep_cxor = 678,
- mep_cnori3 = 680,
- mep_cnori = 682,
- mep_cnor3 = 684,
- mep_cnor = 686,
- mep_cori3 = 688,
- mep_cori = 690,
- mep_cor3 = 692,
- mep_cor = 694,
- mep_candi3 = 696,
- mep_candi = 698,
- mep_cand3 = 700,
- mep_cand = 702,
- mep_csubi3 = 704,
- mep_csubi = 706,
- mep_csub3 = 708,
- mep_csub = 710,
- mep_caddi3 = 712,
- mep_caddi = 714,
- mep_cadd3 = 716,
- mep_cadd = 718
+ mep_fcmpleis = 591,
+ mep_fcmplis = 593,
+ mep_fcmpes = 595,
+ mep_fcmpules = 597,
+ mep_fcmpuls = 599,
+ mep_fcmpues = 601,
+ mep_fcmpus = 603,
+ mep_fcvtsw = 605,
+ mep_ftruncws = 607,
+ mep_fnegs = 609,
+ mep_fabss = 611,
+ mep_fsqrts = 613,
+ mep_fdivs = 615,
+ mep_fmuls = 617,
+ mep_fsubs = 619,
+ mep_fadds = 621,
+ mep_fmovs = 623,
+ mep_cextb = 624,
+ mep_cexth = 625,
+ mep_cextub = 626,
+ mep_cextuh = 627,
+ mep_xmula0 = 628,
+ mep_cmula0 = 629,
+ mep_cneg = 630,
+ mep_cmovh2 = 632,
+ mep_cmovh1 = 633,
+ mep_cmovc2 = 634,
+ mep_cmovc1 = 635,
+ mep_cmov2 = 636,
+ mep_cmov1 = 637,
+ mep_cmovi = 638,
+ mep_cpmov = 640,
+ mep_cmov = 641,
+ mep_csrai3 = 642,
+ mep_csrai = 644,
+ mep_csra3 = 646,
+ mep_csra = 648,
+ mep_csrli3 = 650,
+ mep_csrli = 652,
+ mep_csrl3 = 654,
+ mep_csrl = 656,
+ mep_cslli3 = 658,
+ mep_cslli = 660,
+ mep_csll3 = 662,
+ mep_csll = 664,
+ mep_cxori3 = 666,
+ mep_cxori = 668,
+ mep_cxor3 = 670,
+ mep_cxor = 672,
+ mep_cnori3 = 674,
+ mep_cnori = 676,
+ mep_cnor3 = 678,
+ mep_cnor = 680,
+ mep_cori3 = 682,
+ mep_cori = 684,
+ mep_cor3 = 686,
+ mep_cor = 688,
+ mep_candi3 = 690,
+ mep_candi = 692,
+ mep_cand3 = 694,
+ mep_cand = 696,
+ mep_csubi3 = 698,
+ mep_csubi = 700,
+ mep_csub3 = 702,
+ mep_csub = 704,
+ mep_caddi3 = 706,
+ mep_caddi = 708,
+ mep_cadd3 = 710,
+ mep_cadd = 712
};
#endif /* ! defined (__MEP__) */
@@ -591,12 +591,6 @@ const char *const cgen_intrinsics[] = {
"mep_cpadd3_w",
"mep_cpadd3_h",
"mep_cpadd3_b",
- "mep_cmovh_rn_crm_p0",
- "mep_cmovh_crn_rm_p0",
- "mep_cmovc_rn_ccrm_p0",
- "mep_cmovc_ccrn_rm_p0",
- "mep_cmov_rn_crm_p0",
- "mep_cmov_crn_rm_p0",
"mep_bsrv",
"mep_jsrv",
"mep_synccp",
@@ -6757,7 +6751,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
4 },
- { 646,
+ { 640,
ISA_EXT1,
GROUP_NORMAL,
CODE_FOR_cgen_intrinsic_cpmov_C3,
@@ -6766,7 +6760,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
4 },
- { 646,
+ { 640,
ISA_EXT1|ISA_EXT1,
GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cpmov_P0S_P1,
@@ -7009,7 +7003,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 638,
+ { 632,
ISA_EXT1,
GROUP_NORMAL,
CODE_FOR_cgen_intrinsic_cmovh_rn_crm,
@@ -7018,16 +7012,16 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
4 },
- { 389,
+ { 632,
ISA_EXT1,
GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cmovh_rn_crm_p0,
2,
0,
{ 0, 1 },
- { { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 }, { 32, 48, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
4 },
- { 639,
+ { 633,
ISA_EXT1,
GROUP_NORMAL,
CODE_FOR_cgen_intrinsic_cmovh_crn_rm,
@@ -7036,16 +7030,16 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 390,
+ { 633,
ISA_EXT1,
GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cmovh_crn_rm_p0,
2,
0,
{ 0, 0, 1 },
- { { 32, 48, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 } },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 640,
+ { 634,
ISA_EXT1,
GROUP_NORMAL,
CODE_FOR_cgen_intrinsic_cmovc_rn_ccrm,
@@ -7054,16 +7048,16 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 } },
4 },
- { 391,
+ { 634,
ISA_EXT1,
GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cmovc_rn_ccrm_p0,
2,
0,
{ 0, 1 },
- { { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 }, { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 } },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 } },
4 },
- { 641,
+ { 635,
ISA_EXT1,
GROUP_NORMAL,
CODE_FOR_cgen_intrinsic_cmovc_ccrn_rm,
@@ -7072,16 +7066,16 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 392,
+ { 635,
ISA_EXT1,
GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cmovc_ccrn_rm_p0,
2,
0,
{ 0, 1 },
- { { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 }, { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 } },
+ { { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 642,
+ { 636,
ISA_EXT1,
GROUP_NORMAL,
CODE_FOR_cgen_intrinsic_cmov_rn_crm,
@@ -7090,16 +7084,16 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
4 },
- { 393,
+ { 636,
ISA_EXT1,
GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cmov_rn_crm_p0,
2,
0,
{ 0, 1 },
- { { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 }, { 32, 48, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
4 },
- { 643,
+ { 637,
ISA_EXT1,
GROUP_NORMAL,
CODE_FOR_cgen_intrinsic_cmov_crn_rm,
@@ -7108,16 +7102,16 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 394,
+ { 637,
ISA_EXT1,
GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cmov_crn_rm_p0,
2,
0,
{ 0, 1 },
- { { 32, 48, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 } },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 395,
+ { 389,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bsrv,
@@ -7126,7 +7120,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 396,
+ { 390,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_jsrv,
@@ -7135,7 +7129,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 397,
+ { 391,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_synccp,
@@ -7144,7 +7138,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 398,
+ { 392,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bcpaf,
@@ -7153,7 +7147,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 399,
+ { 393,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bcpat,
@@ -7162,7 +7156,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 400,
+ { 394,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bcpne,
@@ -7171,7 +7165,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 401,
+ { 395,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bcpeq,
@@ -7180,7 +7174,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 402,
+ { 396,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lmcpm1,
@@ -7189,7 +7183,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 403,
+ { 397,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_smcpm1,
@@ -7198,7 +7192,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 404,
+ { 398,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lwcpm1,
@@ -7207,7 +7201,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 405,
+ { 399,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_swcpm1,
@@ -7216,7 +7210,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 406,
+ { 400,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhcpm1,
@@ -7225,7 +7219,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 407,
+ { 401,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_shcpm1,
@@ -7234,7 +7228,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 408,
+ { 402,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbcpm1,
@@ -7243,7 +7237,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 409,
+ { 403,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sbcpm1,
@@ -7252,7 +7246,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 410,
+ { 404,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lmcpm0,
@@ -7261,7 +7255,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 411,
+ { 405,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_smcpm0,
@@ -7270,7 +7264,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 412,
+ { 406,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lwcpm0,
@@ -7279,7 +7273,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 413,
+ { 407,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_swcpm0,
@@ -7288,7 +7282,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 414,
+ { 408,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhcpm0,
@@ -7297,7 +7291,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 415,
+ { 409,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_shcpm0,
@@ -7306,7 +7300,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 416,
+ { 410,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbcpm0,
@@ -7315,7 +7309,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 417,
+ { 411,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sbcpm0,
@@ -7324,7 +7318,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 418,
+ { 412,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lmcpa,
@@ -7333,7 +7327,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 419,
+ { 413,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_smcpa,
@@ -7342,7 +7336,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 420,
+ { 414,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lwcpa,
@@ -7351,7 +7345,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 421,
+ { 415,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_swcpa,
@@ -7360,7 +7354,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 422,
+ { 416,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhcpa,
@@ -7369,7 +7363,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 423,
+ { 417,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_shcpa,
@@ -7378,7 +7372,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 424,
+ { 418,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbcpa,
@@ -7387,7 +7381,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 425,
+ { 419,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sbcpa,
@@ -7396,7 +7390,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 426,
+ { 420,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lmcp16,
@@ -7405,7 +7399,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 427,
+ { 421,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_smcp16,
@@ -7414,7 +7408,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 428,
+ { 422,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lwcp16,
@@ -7423,7 +7417,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 429,
+ { 423,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_swcp16,
@@ -7432,7 +7426,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 430,
+ { 424,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lmcpi,
@@ -7441,7 +7435,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 } },
2 },
- { 431,
+ { 425,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_smcpi,
@@ -7450,7 +7444,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 } },
2 },
- { 432,
+ { 426,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lwcpi,
@@ -7459,7 +7453,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 } },
2 },
- { 433,
+ { 427,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_swcpi,
@@ -7468,7 +7462,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 } },
2 },
- { 434,
+ { 428,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lmcp,
@@ -7477,7 +7471,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 435,
+ { 429,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_smcp,
@@ -7486,7 +7480,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 436,
+ { 430,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lwcp,
@@ -7495,7 +7489,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 437,
+ { 431,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_swcp,
@@ -7504,7 +7498,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 438,
+ { 432,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ssubu,
@@ -7513,7 +7507,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 439,
+ { 433,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_saddu,
@@ -7522,7 +7516,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 440,
+ { 434,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ssub,
@@ -7531,7 +7525,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 441,
+ { 435,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sadd,
@@ -7540,7 +7534,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 442,
+ { 436,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_clipu,
@@ -7549,7 +7543,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 443,
+ { 437,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_clip,
@@ -7558,7 +7552,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 444,
+ { 438,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_maxu,
@@ -7567,7 +7561,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 445,
+ { 439,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_minu,
@@ -7576,7 +7570,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 446,
+ { 440,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_max,
@@ -7585,7 +7579,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 447,
+ { 441,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_min,
@@ -7594,7 +7588,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 448,
+ { 442,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ave,
@@ -7603,7 +7597,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 449,
+ { 443,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_abs,
@@ -7612,7 +7606,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 450,
+ { 444,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ldz,
@@ -7621,7 +7615,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 451,
+ { 445,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_dbreak,
@@ -7630,7 +7624,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 452,
+ { 446,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_dret,
@@ -7639,7 +7633,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 453,
+ { 447,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_divu,
@@ -7648,7 +7642,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 454,
+ { 448,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_div,
@@ -7657,7 +7651,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 455,
+ { 449,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_maddru,
@@ -7666,7 +7660,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 456,
+ { 450,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_maddr,
@@ -7675,7 +7669,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 457,
+ { 451,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_maddu,
@@ -7684,7 +7678,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 458,
+ { 452,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_madd,
@@ -7693,7 +7687,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 459,
+ { 453,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_mulru,
@@ -7702,7 +7696,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 460,
+ { 454,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_mulr,
@@ -7711,7 +7705,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 461,
+ { 455,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_mulu,
@@ -7720,7 +7714,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 462,
+ { 456,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_mul,
@@ -7729,7 +7723,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 463,
+ { 457,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cache,
@@ -7738,7 +7732,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 464,
+ { 458,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_tas,
@@ -7747,7 +7741,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 465,
+ { 459,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_btstm,
@@ -7756,7 +7750,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 466,
+ { 460,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bnotm,
@@ -7765,7 +7759,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_POINTER, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 467,
+ { 461,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bclrm,
@@ -7774,7 +7768,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_POINTER, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 468,
+ { 462,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bsetm,
@@ -7783,7 +7777,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_POINTER, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 469,
+ { 463,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ldcb,
@@ -7792,7 +7786,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 470,
+ { 464,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_stcb,
@@ -7801,7 +7795,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 471,
+ { 465,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_syncm,
@@ -7810,7 +7804,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 472,
+ { 466,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_break,
@@ -7819,7 +7813,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 473,
+ { 467,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_swi,
@@ -7828,7 +7822,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 474,
+ { 468,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sleep,
@@ -7837,7 +7831,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 475,
+ { 469,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_halt,
@@ -7846,7 +7840,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 476,
+ { 470,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_reti,
@@ -7855,7 +7849,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 477,
+ { 471,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ei,
@@ -7864,7 +7858,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 478,
+ { 472,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_di,
@@ -7873,7 +7867,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 479,
+ { 473,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ldc,
@@ -7882,7 +7876,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 32, 16, cgen_regnum_operand_type_DEFAULT, 0 } },
2 },
- { 480,
+ { 474,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ldc_lo,
@@ -7891,7 +7885,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
2 },
- { 481,
+ { 475,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ldc_hi,
@@ -7900,7 +7894,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
2 },
- { 482,
+ { 476,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ldc_lp,
@@ -7909,7 +7903,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
2 },
- { 483,
+ { 477,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_stc,
@@ -7918,7 +7912,7 @@ const struct cgen_insn cgen_insns[] = {
{ 1, 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 32, 16, cgen_regnum_operand_type_DEFAULT, 0 } },
2 },
- { 484,
+ { 478,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_stc_lo,
@@ -7927,7 +7921,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 485,
+ { 479,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_stc_hi,
@@ -7936,7 +7930,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 486,
+ { 480,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_stc_lp,
@@ -7945,7 +7939,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 487,
+ { 481,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_erepeat,
@@ -7954,7 +7948,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 488,
+ { 482,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_repeat,
@@ -7963,7 +7957,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 489,
+ { 483,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ret,
@@ -7972,7 +7966,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
2 },
- { 490,
+ { 484,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_jsr,
@@ -7981,7 +7975,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 491,
+ { 485,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_jmp24,
@@ -7990,7 +7984,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 492,
+ { 486,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_jmp,
@@ -7999,7 +7993,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 494,
+ { 488,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bsr12,
@@ -8008,7 +8002,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
2 },
- { 493,
+ { 487,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bsr24,
@@ -8017,7 +8011,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 495,
+ { 489,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bne,
@@ -8026,7 +8020,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 496,
+ { 490,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_beq,
@@ -8035,7 +8029,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 497,
+ { 491,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bgei,
@@ -8044,7 +8038,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 498,
+ { 492,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_blti,
@@ -8053,7 +8047,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 499,
+ { 493,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bnei,
@@ -8062,7 +8056,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 500,
+ { 494,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_beqi,
@@ -8071,7 +8065,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
4 },
- { 501,
+ { 495,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bnez,
@@ -8080,7 +8074,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
2 },
- { 502,
+ { 496,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_beqz,
@@ -8089,7 +8083,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
2 },
- { 503,
+ { 497,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_bra,
@@ -8098,7 +8092,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
2 },
- { 504,
+ { 498,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_fsft,
@@ -8107,7 +8101,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 505,
+ { 499,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sll3,
@@ -8116,7 +8110,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 506,
+ { 500,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_slli,
@@ -8125,7 +8119,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 507,
+ { 501,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_srli,
@@ -8134,7 +8128,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 508,
+ { 502,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_srai,
@@ -8143,7 +8137,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 509,
+ { 503,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sll,
@@ -8152,7 +8146,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 510,
+ { 504,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_srl,
@@ -8161,7 +8155,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 511,
+ { 505,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sra,
@@ -8170,7 +8164,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 512,
+ { 506,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_xor3,
@@ -8179,7 +8173,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 513,
+ { 507,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_and3,
@@ -8188,7 +8182,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 514,
+ { 508,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_or3,
@@ -8197,7 +8191,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 515,
+ { 509,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_nor,
@@ -8206,7 +8200,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 516,
+ { 510,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_xor,
@@ -8215,7 +8209,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 517,
+ { 511,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_and,
@@ -8224,7 +8218,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 518,
+ { 512,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_or,
@@ -8233,7 +8227,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 519,
+ { 513,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sltu3x,
@@ -8242,7 +8236,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 520,
+ { 514,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_slt3x,
@@ -8251,7 +8245,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 521,
+ { 515,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_add3x,
@@ -8260,7 +8254,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 522,
+ { 516,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sl2ad3,
@@ -8269,7 +8263,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 523,
+ { 517,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sl1ad3,
@@ -8278,7 +8272,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 524,
+ { 518,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sltu3i,
@@ -8287,7 +8281,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 525,
+ { 519,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_slt3i,
@@ -8296,7 +8290,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 526,
+ { 520,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sltu3,
@@ -8305,7 +8299,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 527,
+ { 521,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_slt3,
@@ -8314,7 +8308,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 528,
+ { 522,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_neg,
@@ -8323,7 +8317,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 529,
+ { 523,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sbvck3,
@@ -8332,7 +8326,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 530,
+ { 524,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sub,
@@ -8341,7 +8335,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 531,
+ { 525,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_advck3,
@@ -8350,7 +8344,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 532,
+ { 526,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_add3i,
@@ -8359,7 +8353,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 533,
+ { 527,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_add,
@@ -8368,7 +8362,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 534,
+ { 528,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_add3,
@@ -8377,7 +8371,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 535,
+ { 529,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_movh,
@@ -8386,7 +8380,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 536,
+ { 530,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_movu16,
@@ -8395,7 +8389,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 537,
+ { 531,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_movu24,
@@ -8404,7 +8398,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 539,
+ { 533,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_movi8,
@@ -8413,7 +8407,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 538,
+ { 532,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_movi16,
@@ -8422,7 +8416,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 540,
+ { 534,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_mov,
@@ -8431,7 +8425,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 541,
+ { 535,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ssarb,
@@ -8440,7 +8434,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 542,
+ { 536,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_extuh,
@@ -8449,7 +8443,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
2 },
- { 543,
+ { 537,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_extub,
@@ -8458,7 +8452,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
2 },
- { 544,
+ { 538,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_exth,
@@ -8467,7 +8461,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
2 },
- { 545,
+ { 539,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_extb,
@@ -8476,7 +8470,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
2 },
- { 546,
+ { 540,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lw24,
@@ -8485,7 +8479,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 547,
+ { 541,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sw24,
@@ -8494,7 +8488,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 548,
+ { 542,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhu16,
@@ -8503,7 +8497,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 549,
+ { 543,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbu16,
@@ -8512,7 +8506,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 550,
+ { 544,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lw16,
@@ -8521,7 +8515,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 551,
+ { 545,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lh16,
@@ -8530,7 +8524,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 552,
+ { 546,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lb16,
@@ -8539,7 +8533,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 553,
+ { 547,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sw16,
@@ -8548,7 +8542,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 554,
+ { 548,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sh16,
@@ -8557,7 +8551,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 555,
+ { 549,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sb16,
@@ -8566,7 +8560,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 556,
+ { 550,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhu_tp,
@@ -8575,7 +8569,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 557,
+ { 551,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbu_tp,
@@ -8584,7 +8578,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 558,
+ { 552,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lw_tp,
@@ -8593,7 +8587,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 559,
+ { 553,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lh_tp,
@@ -8602,7 +8596,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 560,
+ { 554,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lb_tp,
@@ -8611,7 +8605,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 561,
+ { 555,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sw_tp,
@@ -8620,7 +8614,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 562,
+ { 556,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sh_tp,
@@ -8629,7 +8623,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 563,
+ { 557,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sb_tp,
@@ -8638,7 +8632,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 564,
+ { 558,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lw_sp,
@@ -8647,7 +8641,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 565,
+ { 559,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sw_sp,
@@ -8656,7 +8650,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
2 },
- { 566,
+ { 560,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhu,
@@ -8665,7 +8659,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 567,
+ { 561,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbu,
@@ -8674,7 +8668,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 568,
+ { 562,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lw,
@@ -8683,7 +8677,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 569,
+ { 563,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lh,
@@ -8692,7 +8686,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 570,
+ { 564,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lb,
@@ -8701,7 +8695,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 571,
+ { 565,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sw,
@@ -8710,7 +8704,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 572,
+ { 566,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sh,
@@ -8719,7 +8713,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 573,
+ { 567,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sb,
@@ -8728,7 +8722,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 574,
+ { 568,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_dsp1,
@@ -8737,7 +8731,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 575,
+ { 569,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_dsp0,
@@ -8746,7 +8740,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 576,
+ { 570,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_dsp,
@@ -8755,7 +8749,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 577,
+ { 571,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_uci,
@@ -8764,7 +8758,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 578,
+ { 572,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhucpm1,
@@ -8773,7 +8767,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 579,
+ { 573,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbucpm1,
@@ -8782,7 +8776,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 580,
+ { 574,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhucpm0,
@@ -8791,7 +8785,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 581,
+ { 575,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbucpm0,
@@ -8800,7 +8794,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 582,
+ { 576,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhucpa,
@@ -8809,7 +8803,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 583,
+ { 577,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbucpa,
@@ -8818,7 +8812,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 584,
+ { 578,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhucp,
@@ -8827,7 +8821,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 585,
+ { 579,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lhcp,
@@ -8836,7 +8830,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 586,
+ { 580,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_shcp,
@@ -8845,7 +8839,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 587,
+ { 581,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbucp,
@@ -8854,7 +8848,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 588,
+ { 582,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_lbcp,
@@ -8863,7 +8857,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 589,
+ { 583,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_sbcp,
@@ -8872,7 +8866,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 590,
+ { 584,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_casw3,
@@ -8881,7 +8875,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 591,
+ { 585,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_cash3,
@@ -8890,7 +8884,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 592,
+ { 586,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_casb3,
@@ -8899,7 +8893,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
4 },
- { 593,
+ { 587,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_prefd,
@@ -8908,7 +8902,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1, 2 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
4 },
- { 594,
+ { 588,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_pref,
@@ -8917,7 +8911,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 595,
+ { 589,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_ldcb_r,
@@ -8926,7 +8920,7 @@ const struct cgen_insn cgen_insns[] = {
{ 0, 1 },
{ { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
2 },
- { 596,
+ { 590,
ISA_MEP|ISA_EXT1,
GROUP_NORMAL|GROUP_VLIW,
CODE_FOR_cgen_intrinsic_stcb_r,
diff --git a/gcc/config/mep/mep-ivc2.cpu b/gcc/config/mep/mep-ivc2.cpu
index 68cab5b..b8bf67e 100644
--- a/gcc/config/mep/mep-ivc2.cpu
+++ b/gcc/config/mep/mep-ivc2.cpu
@@ -314,8 +314,8 @@
(ifield f-ivc2-ccrn-lo))))
)
-(dnop ivc2rm "reg Rm" (all-mep-isas (CDATA REGNUM)) h-gpr f-ivc2-crm)
-(dnop ivc2crn "copro Rn (0-31, 64-bit" (all-mep-isas (CDATA REGNUM)) h-cr64 f-ivc2-crnx)
+(dnop ivc2rm "reg Rm" (all-mep-isas) h-gpr f-ivc2-crm)
+(dnop ivc2crn "copro Rn (0-31, 64-bit" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-crnx)
(dnop ivc2ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn)
(dnop ivc2c3ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn-c3)
@@ -393,7 +393,7 @@
; nnnnmmmm 11110000 0000N000 0000 cmov =crn,rm
(dni cmov-crn-rm-p0
"cmov CRn,Rm"
- (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmov1"))
"cmov $ivc2crn,$ivc2rm"
(+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf00) (f-21 0) (f-ivc2-cmov2 #x00) (f-ivc2-cmov3 0))
(set ivc2crn ivc2rm)
@@ -403,7 +403,7 @@
; nnnnmmmm 11110000 0000N001 0000 cmov =rm,crn
(dni cmov-rn-crm-p0
"cmov Rm,CRn"
- (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmov2"))
"cmov $ivc2rm,$ivc2crn"
(+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf00) (f-21 0) (f-ivc2-cmov2 #x10) (f-ivc2-cmov3 0))
(set ivc2rm ivc2crn)
@@ -413,7 +413,7 @@
; nnnnmmmm 11110000 0000NN10 0000 cmovc =ccrn,rm
(dni cmovc-ccrn-rm-p0
"cmovc CCRn,Rm"
- (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovc1"))
"cmovc $ivc2ccrn,$ivc2rm"
(+ ivc2ccrn ivc2rm (f-ivc2-cmov1 #xf00) (f-ivc2-cmov2 #x20) (f-ivc2-cmov3 0))
(set ivc2ccrn ivc2rm)
@@ -423,7 +423,7 @@
; nnnnmmmm 11110000 0000NN11 0000 cmovc =rm,ccrn
(dni cmovc-rn-ccrm-p0
"cmovc Rm,CCRn"
- (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovc2"))
"cmovc $ivc2rm,$ivc2ccrn"
(+ ivc2ccrn ivc2rm (f-ivc2-cmov1 #xf00) (f-ivc2-cmov2 #x30) (f-ivc2-cmov3 0))
(set ivc2rm ivc2ccrn)
@@ -433,7 +433,7 @@
; nnnnmmmm 11110001 0000N000 0000 cmovh =crn,rm
(dni cmovh-crn-rm-p0
"cmovh CRn,Rm"
- (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovh1"))
"cmovh $ivc2crn,$ivc2rm"
(+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf10) (f-21 0) (f-ivc2-cmov2 #x00) (f-ivc2-cmov3 0))
(set ivc2crn (or (sll (zext DI ivc2rm) 32) (and DI ivc2crn #xffffffff)))
@@ -443,7 +443,7 @@
; nnnnmmmm 11110001 0000N001 0000 cmovh =rm,crn
(dni cmovh-rn-crm-p0
"cmovh Rm,CRn"
- (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovh2"))
"cmovh $ivc2rm,$ivc2crn"
(+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf10) (f-21 0) (f-ivc2-cmov2 #x10) (f-ivc2-cmov3 0))
(set ivc2rm (srl ivc2crn 32))
generated by cgit v1.1 at 2025-08-11 18:48:33 +0000