[RS6000] Tests that use int128_t and -m32

All these tests fail with -m32 due to lack of int128 support, in some
cases with what I thought was not the best error message.  For example
vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
is misleading.  The problem isn't "vector" but "vector __uint128_t".

	* gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128.
	* gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise.
	* gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise.
	* gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
	* gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise.
	* gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise.
	* gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise.
	* gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise.
	* gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.

12 files changed, 12 insertions, 4 deletions

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
index 0b8cfd6..58986d6 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
 
 /* At the time of writing, the number of lxvrbx instructions is
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
index b10d3cb..366a013 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 
 /* Deliberately set optization to zero for this test to confirm
    the lxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
index 52fcf2e..8dfbc79 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
 
 /* At time of writing, we also geenerate a .constrprop copy
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
index 8fc0cc6..87e263c 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 
 /* Deliberately set optization to zero for this test to confirm
    the lxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
index 99f3904..b69a1f3 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 /* Deliberately set optization to zero for this test to confirm
    the stxvr*x instruction is generated. At higher optimization levels
    the instruction we are looking for is sometimes replaced by other
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
index 6e2acf8..76e09fd 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 /* Deliberately set optization to zero for this test to confirm
    the stxvr*x instruction is generated. At higher optimization levels
    the instruction we are looking for is sometimes replaced by other
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
index 7fce6a4..c137ce2 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 
 /* Deliberately set optization to zero for this test to confirm
    the stxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
index 17925c8..7d856e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 
 /* Deliberately set optization to zero for this test to confirm
    the stxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
index 5862517..6ac4ed2 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
 /* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
    supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
index 13b4c8a..05fedf7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
 /* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
    supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
index d58a6b0..6e95269 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
 /* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
    supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
index 9147d67..c2eb53d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
 /* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
    supports the 128-bit integer instructions. */