diff options
| author | Walter Lee <walt@tilera.com> | 2013-03-27 06:17:18 +0000 |
|---|---|---|
| committer | Walter Lee <walt@gcc.gnu.org> | 2013-03-27 06:17:18 +0000 |
| commit | 9332b0d294bb48fa556aebc6c3eba1841f848b8a (patch) | |
| tree | fdc50facd35a4c8e0618e883749914c219141495 | |
| parent | f54ea5dd2e1f7a0e3fe54c16025de04d6054fabd (diff) | |
| download | gcc-9332b0d294bb48fa556aebc6c3eba1841f848b8a.zip gcc-9332b0d294bb48fa556aebc6c3eba1841f848b8a.tar.gz gcc-9332b0d294bb48fa556aebc6c3eba1841f848b8a.tar.bz2 | |
tilegx.md (insn_v1mulu): Fix constraints on input operands.
* config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
input operands.
(insn_v1mulus): Ditto.
(insn_v2muls): Ditto.
From-SVN: r197138
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/tilegx/tilegx.md | 12 |
2 files changed, 13 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6925928..919d3d72 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2013-03-27 Walter Lee <walt@tilera.com> + * config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on + input operands. + (insn_v1mulus): Ditto. + (insn_v2muls): Ditto. + +2013-03-27 Walter Lee <walt@tilera.com> + * config/tilegx/tilegx.h (ASM_OUTPUT_ADDR_VEC_ELT): Delete extra tab. (ASM_OUTPUT_ADDR_DIFF_ELT): Ditto. diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 09bcc5a..9c69170 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -4762,8 +4762,8 @@ (define_expand "insn_v1mulu" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") - (match_operand:DI 2 "reg_or_0_operand" "")] + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")] "" { tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode, @@ -4792,8 +4792,8 @@ (define_expand "insn_v1mulus" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") - (match_operand:DI 2 "reg_or_0_operand" "")] + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")] "" { tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode, @@ -4820,8 +4820,8 @@ (define_expand "insn_v2muls" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") - (match_operand:DI 2 "reg_or_0_operand" "")] + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")] "" { tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode, |