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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2017-04-25 14:04:25 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2017-04-25 14:04:25 +0200 |
| commit | 8b22ef6af9e6e834600a2e1af844d0309774f610 (patch) | |
| tree | ad19a395586b895e2ac3360f4e5428947af5c799 | |
| parent | ad3d6e77aa4b779f8ea8223210b5fc6b3c45c356 (diff) | |
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[ARC] Use ACCL, ACCH registers whenever they are available.
gcc/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_conditional_register_usage): Use ACCL,
ACCH registers whenever they are available.
From-SVN: r247199
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arc/arc.c | 9 |
2 files changed, 14 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e55c5df..5faeb0e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc.c (arc_conditional_register_usage): Use ACCL, + ACCH registers whenever they are available. + +2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc.c (arc_conditional_register_usage): Make D0, D1 double regs fix when not used. diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index dc201ee..0c6b96f 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1585,6 +1585,15 @@ arc_conditional_register_usage (void) SET_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], ACCH_REGNO); SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], ACCL_REGNO); SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], ACCH_REGNO); + SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], ACCL_REGNO); + SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], ACCH_REGNO); + SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], ACCL_REGNO); + SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], ACCH_REGNO); + + /* Allow the compiler to freely use them. */ + fixed_regs[ACCL_REGNO] = 0; + fixed_regs[ACCH_REGNO] = 0; + arc_hard_regno_mode_ok[ACC_REG_FIRST] = D_MODES; } } |