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| author | Ian Bolton <ian.bolton@arm.com> | 2013-07-26 10:54:59 +0000 |
|---|---|---|
| committer | Ian Bolton <ibolton@gcc.gnu.org> | 2013-07-26 10:54:59 +0000 |
| commit | 89fdc743cc79aa02f247cbfa99ba41b4774ed6f8 (patch) | |
| tree | 0329c4017c5deee26e3940936a60eaa08d3d49ac | |
| parent | ee3bf4ae586b6bf6320336999e6e8fd778975b71 (diff) | |
| download | gcc-89fdc743cc79aa02f247cbfa99ba41b4774ed6f8.zip gcc-89fdc743cc79aa02f247cbfa99ba41b4774ed6f8.tar.gz gcc-89fdc743cc79aa02f247cbfa99ba41b4774ed6f8.tar.bz2 | |
AArch64 support for NEG in vector registers for DI and SI mode (part 2)
From-SVN: r201263
| -rw-r--r-- | gcc/ChangeLog | 1 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 773e35c..7d980b3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,7 @@ * config/aarch64/aarch64.md (neg<mode>2): Offer alternative that uses vector registers. + * config/aarch64/iterators.md: Add attributes rtn and vas. 2013-07-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Richard Earnshaw <richard.earnshaw@arm.com> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 76ff15d..3ec889f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -283,6 +283,12 @@ (V2DI "") (V2SF "") (V4SF "") (V2DF "")]) +;; Register Type Name and Vector Arrangement Specifier for when +;; we are doing scalar for DI and SIMD for SI (ignoring all but +;; lane 0). +(define_mode_attr rtn [(DI "d") (SI "")]) +(define_mode_attr vas [(DI "") (SI ".2s")]) + ;; Map a floating point mode to the appropriate register name prefix (define_mode_attr s [(SF "s") (DF "d")]) |