re PR target/18230 (SPARC VIS instructions are not generated by GCC)

	PR target/18230
	* config/sparc/sparc.c (sparc_rtx_costs): Handle the NAND vector
	patterns.
	* config/sparc/sparc.md (V64I): New macro for 64-bit modes.
	(V32I): New macro for 32-bit modes.
	(anddi3, anddi_sp32, anddi_sp64, and_not_di_sp32, and_not_di_sp64,
	iordi3, iordi3_sp32, iordi_sp64, or_not_di_sp32, or_not_di_sp64,
	xordi3, xordi3_sp32, xordi3_sp64, {AND, IOR, XOR} DI splitter,
	xor_not_di_sp32, xordi_not_di_sp64, one_cmpldi2, one_cmpldi_sp32,
	one_cmpldi_sp64): Use V64I instead of DI.
	(andsi3, andsi_sp32, andsi_sp64, and_not_si, iorsi3, or_not_si,
	xorsi3, xor_not_si, one_cmplsi2): Use V32I instead of SI.
	(addv2si3, addv4hi3, addv2hi3): Remove % modifier.
	(nandv64i_vis, nandv32i_vis): New patterns.

Co-Authored-By: Eric Botcazou <ebotcazou@libertysurf.fr>

From-SVN: r90578

21 files changed, 1039 insertions, 155 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 84922f9..7fe8ac6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2004-11-13  James A. Morrison  <phython@gcc.gnu.org>
+            Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	PR target/18230
+	* config/sparc/sparc.c (sparc_rtx_costs): Handle the NAND vector
+	patterns.
+	* config/sparc/sparc.md (V64I): New macro for 64-bit modes.
+	(V32I): New macro for 32-bit modes.
+	(anddi3, anddi_sp32, anddi_sp64, and_not_di_sp32, and_not_di_sp64,
+	iordi3, iordi3_sp32, iordi_sp64, or_not_di_sp32, or_not_di_sp64,
+	xordi3, xordi3_sp32, xordi3_sp64, {AND, IOR, XOR} DI splitter,
+	xor_not_di_sp32, xordi_not_di_sp64, one_cmpldi2, one_cmpldi_sp32,
+	one_cmpldi_sp64): Use V64I instead of DI.
+	(andsi3, andsi_sp32, andsi_sp64, and_not_si, iorsi3, or_not_si,
+	xorsi3, xor_not_si, one_cmplsi2): Use V32I instead of SI.
+	(addv2si3, addv4hi3, addv2hi3): Remove % modifier.
+	(nandv64i_vis, nandv32i_vis): New patterns.
+
 2004-11-12  Mike Stump  <mrs@apple.com>
 
 	* Makefile.in: Add html support.
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 87e30d4..69c3bc5 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -8688,6 +8688,18 @@ sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
 	*total = sparc_costs->int_cmove;
       return false;
 
+    case IOR:
+      /* Handle the NAND vector patterns.  */
+      if (sparc_vector_mode_supported_p (GET_MODE (x))
+	  && GET_CODE (XEXP (x, 0)) == NOT
+	  && GET_CODE (XEXP (x, 1)) == NOT)
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+      else
+        return false;
+
     default:
       return false;
     }
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 6486216..fea0f91 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2208,7 +2208,7 @@
    (set_attr "fptype" "*,*,*,*,*,double,*,*")])
 
 ;; We don't define V1SI because SI should work just fine.
-(define_mode_macro V64 [DF V4HI V8QI V2SI])
+(define_mode_macro V64 [DF V2SI V4HI V8QI])
 (define_mode_macro V32 [SF V2HI V4QI])
 
 (define_insn "*movdi_insn_sp64_vis"
@@ -5929,45 +5929,49 @@
 ;; We define DImode `and' so with DImode `not' we can get
 ;; DImode `andn'.  Other combinations are possible.
 
-(define_expand "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(and:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
+(define_mode_macro V64I [DI V2SI V4HI V8QI])
+(define_mode_macro V32I [SI V2HI V4QI])
+
+(define_expand "and<V64I:mode>3"
+  [(set (match_operand:V64I 0 "register_operand" "")
+	(and:V64I (match_operand:V64I 1 "arith_double_operand" "")
+		  (match_operand:V64I 2 "arith_double_operand" "")))]
   ""
   "")
 
-(define_insn "*anddi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+(define_insn "*and<V64I:mode>3_sp32"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(and:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
+		  (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
   "! TARGET_ARCH64"
   "@
   #
   fand\t%1, %2, %0"
   [(set_attr "type" "*,fga")
    (set_attr "length" "2,*")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*anddi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+(define_insn "*and<V64I:mode>3_sp64"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(and:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
+		  (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
   "TARGET_ARCH64"
   "@
    and\t%1, %2, %0
    fand\t%1, %2, %0"
   [(set_attr "type" "*,fga")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(and:SI (match_operand:SI 1 "arith_operand" "%r,d")
-		(match_operand:SI 2 "arith_operand" "rI,d")))]
+(define_insn "and<V32I:mode>3"
+  [(set (match_operand:V32I 0 "register_operand" "=r,d")
+	(and:V32I (match_operand:V32I 1 "arith_operand" "%r,d")
+		(match_operand:V32I 2 "arith_operand" "rI,d")))]
   ""
   "@
    and\t%1, %2, %0
    fands\t%1, %2, %0"
-  [(set_attr "type" "*,fga")])
+  [(set_attr "type" "*,fga")
+   (set_attr "fptype" "*,single")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -5983,44 +5987,10 @@
   operands[4] = GEN_INT (~INTVAL (operands[2]));
 })
 
-;; Split DImode logical operations requiring two instructions.
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_operator:DI 1 "cc_arithop"	; AND, IOR, XOR
-			   [(match_operand:DI 2 "register_operand" "")
-			    (match_operand:DI 3 "arith_double_operand" "")]))]
-  "! TARGET_ARCH64
-   && reload_completed
-   && ((GET_CODE (operands[0]) == REG
-        && REGNO (operands[0]) < 32)
-       || (GET_CODE (operands[0]) == SUBREG
-           && GET_CODE (SUBREG_REG (operands[0])) == REG
-           && REGNO (SUBREG_REG (operands[0])) < 32))"
-  [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
-   (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
-{
-  operands[4] = gen_highpart (SImode, operands[0]);
-  operands[5] = gen_lowpart (SImode, operands[0]);
-  operands[6] = gen_highpart (SImode, operands[2]);
-  operands[7] = gen_lowpart (SImode, operands[2]);
-#if HOST_BITS_PER_WIDE_INT == 32
-  if (GET_CODE (operands[3]) == CONST_INT)
-    {
-      if (INTVAL (operands[3]) < 0)
-	operands[8] = constm1_rtx;
-      else
-	operands[8] = const0_rtx;
-    }
-  else
-#endif
-    operands[8] = gen_highpart_mode (SImode, DImode, operands[3]);
-  operands[9] = gen_lowpart (SImode, operands[3]);
-})
-
-(define_insn_and_split "*and_not_di_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
-		(match_operand:DI 2 "register_operand" "r,b")))]
+(define_insn_and_split "*and_not_<V64I:mode>_sp32"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(and:V64I (not:V64I (match_operand:V64I 1 "register_operand" "%r,b"))
+		  (match_operand:V64I 2 "register_operand" "r,b")))]
   "! TARGET_ARCH64"
   "@
    #
@@ -6041,68 +6011,70 @@
    operands[8] = gen_lowpart (SImode, operands[2]);"
   [(set_attr "type" "*,fga")
    (set_attr "length" "2,*")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*and_not_di_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
-		(match_operand:DI 2 "register_operand" "r,b")))]
+(define_insn "*and_not_<V64I:mode>_sp64"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(and:V64I (not:V64I (match_operand:V64I 1 "register_operand" "%r,b"))
+		  (match_operand:V64I 2 "register_operand" "r,b")))]
   "TARGET_ARCH64"
   "@
    andn\t%2, %1, %0
    fandnot1\t%1, %2, %0"
   [(set_attr "type" "*,fga")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*and_not_si"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(and:SI (not:SI (match_operand:SI 1 "register_operand" "r,d"))
-		(match_operand:SI 2 "register_operand" "r,d")))]
+(define_insn "*and_not_<V32I:mode>"
+  [(set (match_operand:V32I 0 "register_operand" "=r,d")
+	(and:V32I (not:V32I (match_operand:V32I 1 "register_operand" "%r,d"))
+		  (match_operand:V32I 2 "register_operand" "r,d")))]
   ""
   "@
    andn\t%2, %1, %0
    fandnot1s\t%1, %2, %0"
-  [(set_attr "type" "*,fga")])
+  [(set_attr "type" "*,fga")
+   (set_attr "fptype" "*,single")])
 
-(define_expand "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ior:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
+(define_expand "ior<V64I:mode>3"
+  [(set (match_operand:V64I 0 "register_operand" "")
+	(ior:V64I (match_operand:V64I 1 "arith_double_operand" "")
+		  (match_operand:V64I 2 "arith_double_operand" "")))]
   ""
   "")
 
-(define_insn "*iordi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+(define_insn "*ior<V64I:mode>3_sp32"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(ior:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
+		  (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
   "! TARGET_ARCH64"
   "@
   #
   for\t%1, %2, %0"
   [(set_attr "type" "*,fga")
    (set_attr "length" "2,*")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*iordi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+(define_insn "*ior<V64I:mode>3_sp64"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(ior:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
+		  (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
   "TARGET_ARCH64"
   "@
   or\t%1, %2, %0
   for\t%1, %2, %0"
   [(set_attr "type" "*,fga")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(ior:SI (match_operand:SI 1 "arith_operand" "%r,d")
-		(match_operand:SI 2 "arith_operand" "rI,d")))]
+(define_insn "ior<V32I:mode>3"
+  [(set (match_operand:V32I 0 "register_operand" "=r,d")
+	(ior:V32I (match_operand:V32I 1 "arith_operand" "%r,d")
+		  (match_operand:V32I 2 "arith_operand" "rI,d")))]
   ""
   "@
    or\t%1, %2, %0
    fors\t%1, %2, %0"
-  [(set_attr "type" "*,fga")])
+  [(set_attr "type" "*,fga")
+   (set_attr "fptype" "*,single")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -6118,10 +6090,10 @@
   operands[4] = GEN_INT (~INTVAL (operands[2]));
 })
 
-(define_insn_and_split "*or_not_di_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
-		(match_operand:DI 2 "register_operand" "r,b")))]
+(define_insn_and_split "*or_not_<V64I:mode>_sp32"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(ior:V64I (not:V64I (match_operand:V64I 1 "register_operand" "r,b"))
+		  (match_operand:V64I 2 "register_operand" "r,b")))]
   "! TARGET_ARCH64"
   "@
    #
@@ -6142,58 +6114,59 @@
    operands[8] = gen_lowpart (SImode, operands[2]);"
   [(set_attr "type" "*,fga")
    (set_attr "length" "2,*")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*or_not_di_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
-		(match_operand:DI 2 "register_operand" "r,b")))]
+(define_insn "*or_not_<V64I:mode>_sp64"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(ior:V64I (not:V64I (match_operand:V64I 1 "register_operand" "r,b"))
+		  (match_operand:V64I 2 "register_operand" "r,b")))]
   "TARGET_ARCH64"
   "@
   orn\t%2, %1, %0
   fornot1\t%1, %2, %0"
   [(set_attr "type" "*,fga")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*or_not_si"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(ior:SI (not:SI (match_operand:SI 1 "register_operand" "r,d"))
-		(match_operand:SI 2 "register_operand" "r,d")))]
+(define_insn "*or_not_<V32I:mode>"
+  [(set (match_operand:V32I 0 "register_operand" "=r,d")
+	(ior:V32I (not:V32I (match_operand:V32I 1 "register_operand" "r,d"))
+		  (match_operand:V32I 2 "register_operand" "r,d")))]
   ""
   "@
    orn\t%2, %1, %0
    fornot1s\t%1, %2, %0"
-  [(set_attr "type" "*,fga")])
+  [(set_attr "type" "*,fga")
+   (set_attr "fptype" "*,single")])
 
-(define_expand "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(xor:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
+(define_expand "xor<V64I:mode>3"
+  [(set (match_operand:V64I 0 "register_operand" "")
+	(xor:V64I (match_operand:V64I 1 "arith_double_operand" "")
+		  (match_operand:V64I 2 "arith_double_operand" "")))]
   ""
   "")
 
-(define_insn "*xordi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(xor:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+(define_insn "*xor<V64I:mode>3_sp32"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(xor:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
+		  (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
   "! TARGET_ARCH64"
   "@
   #
   fxor\t%1, %2, %0"
   [(set_attr "type" "*,fga")
    (set_attr "length" "2,*")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*xordi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(xor:DI (match_operand:DI 1 "arith_double_operand" "%rJ,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+(define_insn "*xor<V64I:mode>3_sp64"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(xor:V64I (match_operand:V64I 1 "arith_double_operand" "%rJ,b")
+		  (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
   "TARGET_ARCH64"
   "@
   xor\t%r1, %2, %0
   fxor\t%1, %2, %0"
   [(set_attr "type" "*,fga")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
 (define_insn "*xordi3_sp64_dbl"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -6203,15 +6176,16 @@
     && HOST_BITS_PER_WIDE_INT != 64)"
   "xor\t%1, %2, %0")
 
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(xor:SI (match_operand:SI 1 "arith_operand" "%rJ,d")
-		(match_operand:SI 2 "arith_operand" "rI,d")))]
+(define_insn "xor<V32I:mode>3"
+  [(set (match_operand:V32I 0 "register_operand" "=r,d")
+	(xor:V32I (match_operand:V32I 1 "arith_operand" "%rJ,d")
+		  (match_operand:V32I 2 "arith_operand" "rI,d")))]
   ""
   "@
    xor\t%r1, %2, %0
    fxors\t%1, %2, %0"
-  [(set_attr "type" "*,fga")])
+  [(set_attr "type" "*,fga")
+   (set_attr "fptype" "*,single")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -6241,12 +6215,46 @@
   operands[4] = GEN_INT (~INTVAL (operands[2]));
 })
 
+;; Split DImode logical operations requiring two instructions.
+(define_split
+  [(set (match_operand:V64I 0 "register_operand" "")
+	(match_operator:V64I 1 "cc_arithop"	; AND, IOR, XOR
+			   [(match_operand:V64I 2 "register_operand" "")
+			    (match_operand:V64I 3 "arith_double_operand" "")]))]
+  "! TARGET_ARCH64
+   && reload_completed
+   && ((GET_CODE (operands[0]) == REG
+        && REGNO (operands[0]) < 32)
+       || (GET_CODE (operands[0]) == SUBREG
+           && GET_CODE (SUBREG_REG (operands[0])) == REG
+           && REGNO (SUBREG_REG (operands[0])) < 32))"
+  [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
+   (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
+{
+  operands[4] = gen_highpart (SImode, operands[0]);
+  operands[5] = gen_lowpart (SImode, operands[0]);
+  operands[6] = gen_highpart (SImode, operands[2]);
+  operands[7] = gen_lowpart (SImode, operands[2]);
+#if HOST_BITS_PER_WIDE_INT == 32
+  if (GET_CODE (operands[3]) == CONST_INT && <V64I:MODE>mode == DImode)
+    {
+      if (INTVAL (operands[3]) < 0)
+	operands[8] = constm1_rtx;
+      else
+	operands[8] = const0_rtx;
+    }
+  else
+#endif
+    operands[8] = gen_highpart_mode (SImode, <V64I:MODE>mode, operands[3]);
+  operands[9] = gen_lowpart (SImode, operands[3]);
+})
+
 ;; xnor patterns.  Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
 ;; Combine now canonicalizes to the rightmost expression.
-(define_insn_and_split "*xor_not_di_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(not:DI (xor:DI (match_operand:DI 1 "register_operand" "r,b")
-			(match_operand:DI 2 "register_operand" "r,b"))))]
+(define_insn_and_split "*xor_not_<V64I:mode>_sp32"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(not:V64I (xor:V64I (match_operand:V64I 1 "register_operand" "r,b")
+			    (match_operand:V64I 2 "register_operand" "r,b"))))]
   "! TARGET_ARCH64"
   "@
    #
@@ -6267,28 +6275,29 @@
    operands[8] = gen_lowpart (SImode, operands[2]);"
   [(set_attr "type" "*,fga")
    (set_attr "length" "2,*")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*xor_not_di_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,b")
-			(match_operand:DI 2 "arith_double_operand" "rHI,b"))))]
+(define_insn "*xor_not_<V64I:mode>_sp64"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(not:V64I (xor:V64I (match_operand:V64I 1 "reg_or_0_operand" "rJ,b")
+			    (match_operand:V64I 2 "arith_double_operand" "rHI,b"))))]
   "TARGET_ARCH64"
   "@
   xnor\t%r1, %2, %0
   fxnor\t%1, %2, %0"
   [(set_attr "type" "*,fga")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*xor_not_si"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,d")
-			(match_operand:SI 2 "arith_operand" "rI,d"))))]
+(define_insn "*xor_not_<V32I:mode>"
+  [(set (match_operand:V32I 0 "register_operand" "=r,d")
+	(not:V32I (xor:V32I (match_operand:V32I 1 "reg_or_0_operand" "rJ,d")
+			    (match_operand:V32I 2 "arith_operand" "rI,d"))))]
   ""
   "@
    xnor\t%r1, %2, %0
    fxnors\t%1, %2, %0"
-  [(set_attr "type" "*,fga")])
+  [(set_attr "type" "*,fga")
+   (set_attr "fptype" "*,single")])
 
 ;; These correspond to the above in the case where we also (or only)
 ;; want to set the condition code.  
@@ -6526,15 +6535,15 @@
 
 ;; We cannot use the "not" pseudo insn because the Sun assembler
 ;; does not know how to make it work for constants.
-(define_expand "one_cmpldi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(not:DI (match_operand:DI 1 "register_operand" "")))]
+(define_expand "one_cmpl<V64I:mode>2"
+  [(set (match_operand:V64I 0 "register_operand" "")
+	(not:V64I (match_operand:V64I 1 "register_operand" "")))]
   ""
   "")
 
-(define_insn_and_split "*one_cmpldi2_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(not:DI (match_operand:DI 1 "register_operand" "r,b")))]
+(define_insn_and_split "*one_cmpl<V64I:mode>2_sp32"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(not:V64I (match_operand:V64I 1 "register_operand" "r,b")))]
   "! TARGET_ARCH64"
   "@
    #
@@ -6553,26 +6562,27 @@
    operands[5] = gen_lowpart (SImode, operands[1]);"
   [(set_attr "type" "*,fga")
    (set_attr "length" "2,*")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "*one_cmpldi2_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))]
+(define_insn "*one_cmpl<V64I:mode>2_sp64"
+  [(set (match_operand:V64I 0 "register_operand" "=r,b")
+	(not:V64I (match_operand:V64I 1 "arith_double_operand" "rHI,b")))]
   "TARGET_ARCH64"
   "@
    xnor\t%%g0, %1, %0
    fnot1\t%1, %0"
   [(set_attr "type" "*,fga")
-   (set_attr "fptype" "double")])
+   (set_attr "fptype" "*,double")])
 
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(not:SI (match_operand:SI 1 "arith_operand" "rI,d")))]
+(define_insn "one_cmpl<V32I:mode>2"
+  [(set (match_operand:V32I 0 "register_operand" "=r,d")
+	(not:V32I (match_operand:V32I 1 "arith_operand" "rI,d")))]
   ""
   "@
   xnor\t%%g0, %1, %0
   fnot1s\t%1, %0"
-  [(set_attr "type" "*,fga")])
+  [(set_attr "type" "*,fga")
+   (set_attr "fptype" "*,single")])
 
 (define_insn "*cmp_cc_not"
   [(set (reg:CC 100)
@@ -8873,7 +8883,7 @@
 
 (define_insn "addv2si3"
   [(set (match_operand:V2SI 0 "register_operand" "=e")
-	(plus:V2SI (match_operand:V2SI 1 "register_operand" "%e")
+	(plus:V2SI (match_operand:V2SI 1 "register_operand" "e")
 		   (match_operand:V2SI 2 "register_operand" "e")))]
   "TARGET_VIS"
   "fpadd32\t%1, %2, %0"
@@ -8882,7 +8892,7 @@
 
 (define_insn "addv4hi3"
   [(set (match_operand:V4HI 0 "register_operand" "=e")
-	 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%e")
+	 (plus:V4HI (match_operand:V4HI 1 "register_operand" "e")
 		    (match_operand:V4HI 2 "register_operand" "e")))]
   "TARGET_VIS"
   "fpadd16\t%1, %2, %0"
@@ -8893,7 +8903,7 @@
 
 (define_insn "addv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=f")
-	(plus:V2HI (match_operand:V2HI 1 "register_operand" "%f")
+	(plus:V2HI (match_operand:V2HI 1 "register_operand" "f")
 		   (match_operand:V2HI 2 "register_operand" "f")))]
   "TARGET_VIS"
   "fpadd16s\t%1, %2, %0"
@@ -8928,3 +8938,26 @@
   "fpsub16s\t%1, %2, %0"
   [(set_attr "type" "fga")
    (set_attr "fptype" "single")])
+
+;; All other logical instructions have integer equivalents so they
+;; are defined together.
+
+;; (ior (not (op1)) (not (op2))) is the canonical form of NAND.
+
+(define_insn "*nand<V64mode>_vis"
+  [(set (match_operand:V64 0 "register_operand" "=e")
+	(ior:V64 (not:V64 (match_operand:V64 1 "register_operand" "e"))
+		 (not:V64 (match_operand:V64 2 "register_operand" "e"))))]
+  "TARGET_VIS"
+  "fnand\t%1, %2, %0"
+  [(set_attr "type" "fga")
+   (set_attr "fptype" "double")])
+
+(define_insn "*nand<V32mode>_vis"
+  [(set (match_operand:V32 0 "register_operand" "=f")
+	 (ior:V32 (not:V32 (match_operand:V32 1 "register_operand" "f"))
+		  (not:V32 (match_operand:V32 2 "register_operand" "f"))))]
+  "TARGET_VIS"
+  "fnands\t%1, %2, %0"
+  [(set_attr "type" "fga")
+   (set_attr "fptype" "single")])
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a8ea52e..851443f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2004-11-13  James A. Morrison  <phython@gcc.gnu.org>
+
+	* gcc.target/sparc/fand.c, gcc.target/sparc/fands,
+	gcc.target/sparc/fnand.c, gcc.target/sparc/fnands.c,
+	gcc.target/sparc/fxor.c, gcc.target/sparc/fxors.c,
+	gcc.target/sparc/fxnor.c, gcc.target/sparc/fxnors.c,
+	gcc.target/sparc/fandnot.c, gcc.target/sparc/fandnots.c,
+	gcc.target/sparc/fornot.c, gcc.target/sparc/fornots.c,
+	gcc.target/sparc/fnot.c, gcc.target/sparc/fnots.c,
+	gcc.target/sparc/for.c, gcc.target/sparc/fors.c,
+	gcc.target/sparc/combined-1.c: New tests.
+
 2004-11-12  Ziemowit Laski  <zlaski@apple.com>
 
 	* objc.dg/const-str-8.m, objc.dg/const-str-9.m:
diff --git a/gcc/testsuite/gcc.target/sparc/combined-1.c b/gcc/testsuite/gcc.target/sparc/combined-1.c
new file mode 100644
index 0000000..5f19db3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/combined-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec16 fun16(vec16 a, vec16 b)
+{
+  return (~a & b) + (b | a) - (a ^ b);
+}
+
+vec32 fun32(vec32 a, vec32 b)
+{
+  return (~a & b) + (b | a) - (a ^ b);
+}
+
+/* This should be transformed into ~b & a.  */
+vec16 fun16b(vec16 a, vec16 b)
+{
+  return (a & ~b) + (b | a) - (a ^ b);
+}
+
+vec32 fun32b(vec32 a, vec32 b)
+{
+  return (a & ~b) + (b | a) - (a ^ b);
+}
+
+/* { dg-final { scan-assembler-times "fandnot1\t%" 4 } } */
+/* { dg-final { scan-assembler-times "for\t%" 4 } } */
+/* { dg-final { scan-assembler-times "fpadd" 4 } } */
+/* { dg-final { scan-assembler-times "fxor\t%" 4 } } */
+/* { dg-final { scan-assembler-times "fpsub" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fand.c b/gcc/testsuite/gcc.target/sparc/fand.c
new file mode 100644
index 0000000..3194c92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fand.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () & foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a & b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () & foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a & b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () & foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a & b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fand\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fandnot.c b/gcc/testsuite/gcc.target/sparc/fandnot.c
new file mode 100644
index 0000000..41db849
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fandnot.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () & foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~a & b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () & foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~a & b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 () & foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~a & b;
+}
+#endif
+
+
+/* This should be transformed into ~b & a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () & ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a & ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () & ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a & ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () & ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a & ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fandnot1\t%" 6 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fandnots.c b/gcc/testsuite/gcc.target/sparc/fandnots.c
new file mode 100644
index 0000000..7a5ed24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fandnots.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () & foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () & foo1_16 ();
+}
+
+
+/* This should be transformed into ~b & a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () & ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () & ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fandnot1s\t%" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fands.c b/gcc/testsuite/gcc.target/sparc/fands.c
new file mode 100644
index 0000000..f924f45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fands.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () & foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () & foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fands\t%" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fnand.c b/gcc/testsuite/gcc.target/sparc/fnand.c
new file mode 100644
index 0000000..89fe869
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnand.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo2_16 ());
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () & foo2_32 ());
+}
+
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo2_16 ();
+}
+
+vec32 fun32b(void)
+{
+  return ~foo1_32 () | ~foo2_32 ();
+}
+
+/* { dg-final { scan-assembler-times "fnand\t%" 6 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fnands.c b/gcc/testsuite/gcc.target/sparc/fnands.c
new file mode 100644
index 0000000..05d6c47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnands.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo1_16 ());
+}
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fnands\t%" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fnot.c b/gcc/testsuite/gcc.target/sparc/fnot.c
new file mode 100644
index 0000000..e6f98d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnot.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern void foo2_8(vec8);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a)
+{
+  foo2_8 (~a);
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern void foo2_16(vec8);
+
+
+vec16 fun16(void)
+{
+  return ~foo1_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a)
+{
+  foo2_16 (~a);
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern void foo2_32(vec8);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a)
+{
+  foo2_32 (~a);
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fnot1\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fnots.c b/gcc/testsuite/gcc.target/sparc/fnots.c
new file mode 100644
index 0000000..f50eb0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnots.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 ();
+}
+
+extern vec16 foo1_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fnot1s\t%" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/for.c b/gcc/testsuite/gcc.target/sparc/for.c
new file mode 100644
index 0000000..7348dce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/for.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () | foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a | b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () | foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a | b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () | foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a | b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "for\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fornot.c b/gcc/testsuite/gcc.target/sparc/fornot.c
new file mode 100644
index 0000000..09fdb4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fornot.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () | foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~a | b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () | foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~a | b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 () | foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~a | b;
+}
+#endif
+
+
+/* This should be transformed into ~b | a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () | ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a | ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () | ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a | ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () | ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a | ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fornot1\t%" 6 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fornots.c b/gcc/testsuite/gcc.target/sparc/fornots.c
new file mode 100644
index 0000000..db29a99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fornots.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () | foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () | foo1_16 ();
+}
+
+
+/* This should be transformed into ~b | a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () | ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fornot1s\t%" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fors.c b/gcc/testsuite/gcc.target/sparc/fors.c
new file mode 100644
index 0000000..0afdd4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fors.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () | foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () | foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fors\t%" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fxnor.c b/gcc/testsuite/gcc.target/sparc/fxnor.c
new file mode 100644
index 0000000..a685e08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fxnor.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () ^ foo2_8 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () ^ foo2_16 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () ^ foo2_32 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+
+/* This should be transformed into ~(b ^ a).  */
+vec8 fun8b(void)
+{
+  return foo1_8 () ^ ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () ^ ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () ^ ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fxnor\t%" 6 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fxnors.c b/gcc/testsuite/gcc.target/sparc/fxnors.c
new file mode 100644
index 0000000..29775cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fxnors.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () ^ foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () ^ foo1_16 ());
+}
+
+
+/* This should be transformed into ~(b ^ a).  */
+vec8 fun8b(void)
+{
+  return foo1_8 () ^ ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () ^ ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fxnors\t%" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fxor.c b/gcc/testsuite/gcc.target/sparc/fxor.c
new file mode 100644
index 0000000..581b37b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fxor.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () ^ foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a ^ b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () ^ foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a ^ b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () ^ foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a ^ b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fxor\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fxors.c b/gcc/testsuite/gcc.target/sparc/fxors.c
new file mode 100644
index 0000000..5da017a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fxors.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () ^ foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () ^ foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fxors\t%" 2 } } */