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authorAndrew Pinski <apinski@marvell.com>2020-01-17 06:54:53 +0000
committerAndrew Pinski <apinski@marvell.com>2020-01-22 01:31:54 +0000
commit87ca615aa6f400c64d0bf13088c0ffdd14e22830 (patch)
treeba64ee35b1ca11859330206faebda0f656292d28
parentac68e287fc2e939ae6b45ba7ff04e493982b7f62 (diff)
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Fix target/93119 (aarch64): ICE with traditional TLS support on ILP32
The problem here was g:23b88fda665d2f995c was not a complete fix for supporting tranditional TLS on ILP32. So the problem here is a couple of things, first __tls_get_addr call will return a C pointer value so we need to use ptr_mode when we are creating the call. Then we need to convert back that register to the correct mode, either zero extending it or just creating a move instruction. Also symbol_ref can either be in SImode or DImode. So we need to allow both modes. Built and tested on aarch64-linux-gnu with no regressions. Also built a full toolchain (including glibc) defaulting to traditional TLS that targets ilp32 and lp64. ChangeLog: PR target/93119 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0 as PTR mode. Have operand 1 as being modeless, it can be P mode. (*tlsgd_small_<mode>): Likewise. * config/aarch64/aarch64.c (aarch64_load_symref_appropriately) <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode register. Convert that register back to dest using convert_mode.
-rw-r--r--gcc/ChangeLog11
-rw-r--r--gcc/config/aarch64/aarch64.c17
-rw-r--r--gcc/config/aarch64/aarch64.md8
-rw-r--r--gcc/testsuite/ChangeLog5
-rw-r--r--gcc/testsuite/gcc.target/aarch64/pr93119.c10
5 files changed, 43 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2f6e603..85cf788 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-01-21 Andrew Pinski <apinski@marvell.com>
+
+ PR target/9311
+ * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
+ as PTR mode. Have operand 1 as being modeless, it can be P mode.
+ (*tlsgd_small_<mode>): Likewise.
+ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
+ <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
+ register. Convert that register back to dest using convert_mode.
+
+
2020-01-21 Jim Wilson <jimw@sifive.com>
* config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index ef037e2..9acf33d 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2607,11 +2607,16 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
case SYMBOL_SMALL_TLSGD:
{
rtx_insn *insns;
- machine_mode mode = GET_MODE (dest);
- rtx result = gen_rtx_REG (mode, R0_REGNUM);
+ /* The return type of __tls_get_addr is the C pointer type
+ so use ptr_mode. */
+ rtx result = gen_rtx_REG (ptr_mode, R0_REGNUM);
+ rtx tmp_reg = dest;
+
+ if (GET_MODE (dest) != ptr_mode)
+ tmp_reg = can_create_pseudo_p () ? gen_reg_rtx (ptr_mode) : result;
start_sequence ();
- if (TARGET_ILP32)
+ if (ptr_mode == SImode)
aarch64_emit_call_insn (gen_tlsgd_small_si (result, imm));
else
aarch64_emit_call_insn (gen_tlsgd_small_di (result, imm));
@@ -2619,7 +2624,11 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
end_sequence ();
RTL_CONST_CALL_P (insns) = 1;
- emit_libcall_block (insns, dest, result, imm);
+ emit_libcall_block (insns, tmp_reg, result, imm);
+ /* Convert back to the mode of the dest adding a zero_extend
+ from SImode (ptr_mode) to DImode (Pmode). */
+ if (dest != tmp_reg)
+ convert_move (dest, tmp_reg, true);
return;
}
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 86c2cdf..55dde54 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -6755,10 +6755,10 @@
;; instructions in the TLS stubs, in order to enable linker relaxation.
;; Therefore we treat the stubs as an atomic sequence.
(define_expand "tlsgd_small_<mode>"
- [(parallel [(set (match_operand 0 "register_operand")
+ [(parallel [(set (match_operand:PTR 0 "register_operand")
(call (mem:DI (match_dup 2)) (const_int 1)))
(unspec:DI [(const_int 0)] UNSPEC_CALLEE_ABI)
- (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref")] UNSPEC_GOTSMALLTLS)
+ (unspec:DI [(match_operand 1 "aarch64_valid_symref")] UNSPEC_GOTSMALLTLS)
(clobber (reg:DI LR_REGNUM))])]
""
{
@@ -6766,10 +6766,10 @@
})
(define_insn "*tlsgd_small_<mode>"
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand:PTR 0 "register_operand" "")
(call (mem:DI (match_operand:DI 2 "" "")) (const_int 1)))
(unspec:DI [(const_int 0)] UNSPEC_CALLEE_ABI)
- (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS)
+ (unspec:DI [(match_operand 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS)
(clobber (reg:DI LR_REGNUM))
]
""
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f72c987..1be1b59 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-21 Andrew Pinski <apinski@marvell.com>
+
+ PR target/93119
+ * gcc.target/aarch64/pr93119.c: New test.
+
2020-01-22 Joseph Myers <joseph@codesourcery.com>
PR c/93348
diff --git a/gcc/testsuite/gcc.target/aarch64/pr93119.c b/gcc/testsuite/gcc.target/aarch64/pr93119.c
new file mode 100644
index 0000000..93fa80e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr93119.c
@@ -0,0 +1,10 @@
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-mtls-dialect=trad -fpic" } */
+
+__thread int g_tlsdata;
+
+int func1()
+{
+ g_tlsdata++;
+ return g_tlsdata;
+}