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authorRichard Earnshaw <rearnsha@arm.com>2002-09-18 14:01:58 +0000
committerRichard Earnshaw <rearnsha@gcc.gnu.org>2002-09-18 14:01:58 +0000
commit872e50d35b5f4ec30a769823bd5b6ed84da89b39 (patch)
tree9efda27f308a0c48151a4887a8278a7a67763246
parentdd29188b820fc8bfae31d7aa4bb364858de1126f (diff)
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re PR rtl-optimization/7967 (optimization produces wrong code (ARM))
PR optimization/7967 * arm.md (ne_zeroextractsi): Add clobber of the condition code register. From-SVN: r57278
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/arm/arm.md3
2 files changed, 8 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fcf11dd..ee2543a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2002-09-18 Richard Earnshaw (reanrsha@arm.com)
+
+ PR optimization/7967
+ * arm.md (ne_zeroextractsi): Add clobber of the condition code
+ register.
+
2002-09-18 Kazu Hirata <kazu@cs.umass.edu>
* config/s390/s390.c: Follow spelling convention.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index b56955d..a830462 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1838,7 +1838,8 @@
(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n"))
- (const_int 0)))]
+ (const_int 0)))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM
&& (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
&& INTVAL (operands[2]) > 0