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| author | Alexander Monakov <amonakov@gcc.gnu.org> | 2011-10-19 16:46:44 +0400 |
|---|---|---|
| committer | Alexander Monakov <amonakov@gcc.gnu.org> | 2011-10-19 16:46:44 +0400 |
| commit | 854b5fd7b52ae803fd48eb942095a75fa6f910a8 (patch) | |
| tree | 431a3f95c56d18fcbb0c246f32e76182005871da | |
| parent | 9b6ab3c0591fd583915861cfd1d27183873221e8 (diff) | |
| download | gcc-854b5fd7b52ae803fd48eb942095a75fa6f910a8.zip gcc-854b5fd7b52ae803fd48eb942095a75fa6f910a8.tar.gz gcc-854b5fd7b52ae803fd48eb942095a75fa6f910a8.tar.bz2 | |
re PR rtl-optimization/50340 (Fails to build SPEC 2000 176.gcc)
2011-10-19 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/50340
* sel-sched-ir.c (update_target_availability): LHS register
availability is not known if the unavailable LHS of the other
expression is a different register.
* gcc.dg/pr50340.c: New.
From-SVN: r180186
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/sel-sched-ir.c | 5 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr50340.c | 46 |
4 files changed, 63 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 115c5d9..4a3bc75 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2011-10-19 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/50340 + * sel-sched-ir.c (update_target_availability): LHS register + availability is not known if the unavailable LHS of the other + expression is a different register. + 2011-10-19 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> PR target/50310 diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c index 4878460..dacee0b 100644 --- a/gcc/sel-sched-ir.c +++ b/gcc/sel-sched-ir.c @@ -1745,6 +1745,11 @@ update_target_availability (expr_t to, expr_t from, insn_t split_point) else EXPR_TARGET_AVAILABLE (to) = -1; } + else if (EXPR_TARGET_AVAILABLE (from) == 0 + && EXPR_LHS (from) + && REG_P (EXPR_LHS (from)) + && REGNO (EXPR_LHS (to)) != REGNO (EXPR_LHS (from))) + EXPR_TARGET_AVAILABLE (to) = -1; else EXPR_TARGET_AVAILABLE (to) &= EXPR_TARGET_AVAILABLE (from); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2ed5429..72c85cd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2011-10-19 Alexander Monakov <amonakov@ispras.ru> + + PR rtl-optimization/50340 + * gcc.dg/pr50340.c: New. + 2011-10-18 Andrew Stubbs <ams@codesourcery.com> PR tree-optimization/50717 diff --git a/gcc/testsuite/gcc.dg/pr50340.c b/gcc/testsuite/gcc.dg/pr50340.c new file mode 100644 index 0000000..1843036 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr50340.c @@ -0,0 +1,46 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O3 -fselective-scheduling2 -funroll-loops" } */ +extern int mode_size[]; +typedef unsigned HARD_REG_SET[ ((64 + 32 - 1) / 32) ]; +enum reload_type { + RELOAD_FOR_INPUT, + RELOAD_FOR_OUTPUT, + RELOAD_FOR_INSN, + RELOAD_FOR_INPUT_ADDRESS, + RELOAD_FOR_OUTPUT_ADDRESS, + RELOAD_FOR_OPERAND_ADDRESS, + RELOAD_FOR_OPADDR_ADDR, + RELOAD_OTHER, + RELOAD_FOR_OTHER_ADDRESS +}; +static HARD_REG_SET reload_reg_used; +static HARD_REG_SET reload_reg_used_in_input_addr[10]; +static HARD_REG_SET reload_reg_used_in_output_addr[10]; +static HARD_REG_SET reload_reg_used_in_input[10]; +static HARD_REG_SET reload_reg_used_in_output[10]; +static HARD_REG_SET reload_reg_used_in_op_addr; +static HARD_REG_SET reload_reg_used_in_op_addr_reload; +static HARD_REG_SET reload_reg_used_in_insn; +static HARD_REG_SET reload_reg_used_in_other_addr; +static HARD_REG_SET reload_reg_used_at_all; +void __attribute__((cold)) mark_reload_reg_in_use (regno, opnum, type, mode) +{ + int nregs = regno ? 1 : mode_size[mode]; + int i; + for (i = regno; i < nregs + regno; i++) + { + switch (type) + { + case RELOAD_OTHER: reload_reg_used[i / 32u] |= 1 << i % 32u; break; + case RELOAD_FOR_INPUT_ADDRESS: reload_reg_used_in_input_addr[opnum][i / 32u] |= 1 << i % 32u; break; + case RELOAD_FOR_OUTPUT_ADDRESS: reload_reg_used_in_output_addr[opnum][i / 32u] |= 1 << i % 32u; break; + case RELOAD_FOR_OPERAND_ADDRESS: reload_reg_used_in_op_addr[i / 32u] |= 1 << i % 32u; break; + case RELOAD_FOR_OPADDR_ADDR: reload_reg_used_in_op_addr_reload[i / 32u] |= 1 << i % 32u; break; + case RELOAD_FOR_OTHER_ADDRESS: reload_reg_used_in_other_addr[i / 32u] |= 1; break; + case RELOAD_FOR_INPUT: reload_reg_used_in_input[opnum][i / 32u] |= 1 << i % 32u; break; + case RELOAD_FOR_OUTPUT: reload_reg_used_in_output[opnum][i / 32u] |= 1 << i % 32u; break; + case RELOAD_FOR_INSN: reload_reg_used_in_insn[i / 32u] |= 1 << i % 32u; + } + reload_reg_used_at_all[i / 32u] |= 1 << i; + } +} |