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author | H.J. Lu <hjl@gcc.gnu.org> | 2013-12-26 06:47:15 -0800 |
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committer | H.J. Lu <hjl@gcc.gnu.org> | 2013-12-26 06:47:15 -0800 |
commit | 806ac507476f414a3accae49e8ced8789a2190a3 (patch) | |
tree | dab18eee2c107ed78adf00ed489bb834f55a355f | |
parent | 1879e97f6cf296fb0a30e85350b79f73fc58aad5 (diff) | |
download | gcc-806ac507476f414a3accae49e8ced8789a2190a3.zip gcc-806ac507476f414a3accae49e8ced8789a2190a3.tar.gz gcc-806ac507476f414a3accae49e8ced8789a2190a3.tar.bz2 |
Map "arch=corei7"/"arch=nehalem" to M_INTEL_COREI7
After Intel processor name cleanup,
__attribute__ ((target("arch=corei7"))) is translated to PROCESSOR_NEHALEM
and mapped to M_INTEL_COREI7_NEHALEM.
__attribute__ ((target("arch=corei7")))
used to cover M_INTEL_COREI7_XXXX. Now it only covers M_INTEL_COREI7_NEHALEM.
We have PROCESSOR_SANDYBRIDGE and PROCESSOR_HASWELL. But there is nothing
to mark Westmere and Ivy Bridge. Since function versioning doesn't support
extra ISAs in Westmere and Ivy Bridge, we don't lose anything. The solution
is to map
__attribute__ ((target("arch=corei7")))
and
__attribute__ ((target("arch=nehalem")))
to M_INTEL_COREI7.
gcc/
PR target/59601
* config/i386/i386.c (get_builtin_code_for_version): Map
PROCESSOR_NEHALEM to "corei7".
gcc/testsuite/
PR target/59601
* g++.dg/ext/mv14.C: New tests.
* g++.dg/ext/mv15.C: Likewise.
From-SVN: r206212
-rw-r--r-- | gcc/ChangeLog | 16 | ||||
-rw-r--r-- | gcc/config/i386/i386.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/testsuite/g++.dg/ext/mv14.C | 40 | ||||
-rw-r--r-- | gcc/testsuite/g++.dg/ext/mv15.C | 40 |
5 files changed, 102 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 52a74f0..186fa1c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,10 +1,16 @@ +2013-12-26 H.J. Lu <hongjiu.lu@intel.com> + + PR target/59601 + * config/i386/i386.c (get_builtin_code_for_version): Map + PROCESSOR_NEHALEM to "corei7". + 2013-12-26 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> - * config/i386/i386.c (get_builtin_code_for_version): Rename AMD - CPU names M_AMD_BOBCAT to M_AMD_BTVER1 and M_AMD_JAGUAR - to M_AMD_BTVER2. - (processor_model): Likewise. - (arch_names_table): Likewise. + * config/i386/i386.c (get_builtin_code_for_version): Rename AMD + CPU names M_AMD_BOBCAT to M_AMD_BTVER1 and M_AMD_JAGUAR + to M_AMD_BTVER2. + (processor_model): Likewise. + (arch_names_table): Likewise. 2013-12-26 Uros Bizjak <ubizjak@gmail.com> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 33e6495..71063bb 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -30010,7 +30010,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) priority = P_PROC_SSSE3; break; case PROCESSOR_NEHALEM: - arg_str = "nehalem"; + /* We translate "arch=corei7" and "arch=nehelam" to + "corei7" so that it will be mapped to M_INTEL_COREI7 + as cpu type to cover all M_INTEL_COREI7_XXXs. */ + arg_str = "corei7"; priority = P_PROC_SSE4_2; break; case PROCESSOR_SANDYBRIDGE: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index aede8f8..51be98c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2013-12-26 Uros Bizjak <ubizjak@gmail.com> + H.J. Lu <hongjiu.lu@intel.com> + + PR target/59601 + * g++.dg/ext/mv14.C: New tests. + * g++.dg/ext/mv15.C: Likewise. + 2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org> PR target/59422 diff --git a/gcc/testsuite/g++.dg/ext/mv14.C b/gcc/testsuite/g++.dg/ext/mv14.C new file mode 100644 index 0000000..e36e08d --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/mv14.C @@ -0,0 +1,40 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run { target i?86-*-* x86_64-*-* } } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O2 -fPIC" } */ + +#include <assert.h> + +/* Default version. */ +int foo (); // Extra declaration that is merged with the second one. +int foo () __attribute__ ((target("default"))); + +int foo () __attribute__ ((target("arch=corei7"))); + +int (*p)() = &foo; +int main () +{ + int val = foo (); + assert (val == (*p)()); + + /* Check in the exact same order in which the dispatching + is expected to happen. */ + if (__builtin_cpu_is ("corei7")) + assert (val == 5); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("arch=corei7"))) +foo () +{ + return 5; +} diff --git a/gcc/testsuite/g++.dg/ext/mv15.C b/gcc/testsuite/g++.dg/ext/mv15.C new file mode 100644 index 0000000..42e39d2 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/mv15.C @@ -0,0 +1,40 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run { target i?86-*-* x86_64-*-* } } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O2 -fPIC" } */ + +#include <assert.h> + +/* Default version. */ +int foo (); // Extra declaration that is merged with the second one. +int foo () __attribute__ ((target("default"))); + +int foo () __attribute__ ((target("arch=nehalem"))); + +int (*p)() = &foo; +int main () +{ + int val = foo (); + assert (val == (*p)()); + + /* Check in the exact same order in which the dispatching + is expected to happen. */ + if (__builtin_cpu_is ("corei7")) + assert (val == 5); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("arch=nehalem"))) +foo () +{ + return 5; +} |