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| author | Kazu Hirata <kazu@hxi.com> | 2002-02-02 21:15:24 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@gcc.gnu.org> | 2002-02-02 21:15:24 +0000 |
| commit | 7a27efc4eb366a39d5c0a4a8dda6f0cbe2c91826 (patch) | |
| tree | 4e624b7586c56108a963c99201cd39bfc649604e | |
| parent | 9b8b2fcfda6acd6cba19691a3b1d966c8299efcc (diff) | |
| download | gcc-7a27efc4eb366a39d5c0a4a8dda6f0cbe2c91826.zip gcc-7a27efc4eb366a39d5c0a4a8dda6f0cbe2c91826.tar.gz gcc-7a27efc4eb366a39d5c0a4a8dda6f0cbe2c91826.tar.bz2 | |
* config/h8300/h8300.md: Fix formatting.
From-SVN: r49448
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/h8300/h8300.md | 59 |
2 files changed, 28 insertions, 35 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b6bff10..edd2179 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2002-02-02 Kazu Hirata <kazu@hxi.com> + * config/h8300/h8300.md: Fix formatting. + +2002-02-02 Kazu Hirata <kazu@hxi.com> + * config/h8300/h8300.md (one_cmpl patterns): Tighten the predicates of operands[1]. Split the patterns for each processor variant. diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index da0f6f1..35f2750 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -1887,25 +1887,22 @@ (define_expand "ashlsi3" [(set (match_operand:SI 0 "register_operand" "") - (ashift:SI - (match_operand:SI 1 "general_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + (ashift:SI (match_operand:SI 1 "general_operand" "") + (match_operand:QI 2 "nonmemory_operand" "")))] "" "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;") (define_expand "lshrsi3" [(set (match_operand:SI 0 "register_operand" "") - (lshiftrt:SI - (match_operand:SI 1 "general_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + (lshiftrt:SI (match_operand:SI 1 "general_operand" "") + (match_operand:QI 2 "nonmemory_operand" "")))] "" "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;") (define_expand "ashrsi3" [(set (match_operand:SI 0 "register_operand" "") - (ashiftrt:SI - (match_operand:SI 1 "general_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + (ashiftrt:SI (match_operand:SI 1 "general_operand" "") + (match_operand:QI 2 "nonmemory_operand" "")))] "" "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;") @@ -2152,9 +2149,8 @@ (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") - (ior:HI - (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) - (match_operand:HI 2 "register_operand" "0")))] + (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) + (match_operand:HI 2 "register_operand" "0")))] "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[0]) != REGNO (operands[1])" @@ -2164,9 +2160,8 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI - (zero_extend:SI (match_operand:HI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "0")))] + (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "0")))] "(TARGET_H8300H || TARGET_H8300S) && REG_P (operands[0]) && REG_P (operands[1]) @@ -2177,9 +2172,8 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI - (zero_extend:SI (match_operand:QI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "0")))] + (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "0")))] "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[0]) != REGNO (operands[1])" @@ -2189,9 +2183,8 @@ (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") - (xor:HI - (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) - (match_operand:HI 2 "register_operand" "0")))] + (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) + (match_operand:HI 2 "register_operand" "0")))] "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[0]) != REGNO (operands[1])" @@ -2201,9 +2194,8 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (xor:SI - (zero_extend:SI (match_operand:HI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "0")))] + (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "0")))] "(TARGET_H8300H || TARGET_H8300S) && REG_P (operands[0]) && REG_P (operands[1]) @@ -2214,9 +2206,8 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (xor:SI - (zero_extend:SI (match_operand:QI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "0")))] + (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "0")))] "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[0]) != REGNO (operands[1])" @@ -2226,10 +2217,9 @@ (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") - (ior:HI - (zero_extend:HI (match_operand:QI 1 "register_operand" "0")) - (ashift:HI (match_operand:HI 2 "register_operand" "r") - (const_int 8))))] + (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0")) + (ashift:HI (match_operand:HI 2 "register_operand" "r") + (const_int 8))))] "REG_P (operands[0]) && REG_P (operands[2]) && REGNO (operands[0]) != REGNO (operands[2])" @@ -2239,10 +2229,9 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI - (zero_extend:SI (match_operand:HI 1 "register_operand" "0")) - (ashift:SI (match_operand:SI 2 "register_operand" "r") - (const_int 16))))] + (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0")) + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 16))))] "(TARGET_H8300H || TARGET_H8300S) && REG_P (operands[0]) && REG_P (operands[2]) |