mips.h (ISA_HAS_BADDU): New macro.

	* config/mips/mips.h (ISA_HAS_BADDU): New macro.
	* config/mips/mips.md (*baddu_si_eb, *baddu_si_el,
	*baddu_di<mode>): New patterns.

testsuite/
	* gcc.target/mips/octeon-baddu-1.c: New test.

From-SVN: r140556

5 files changed, 75 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d7d57c9..feee648 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2008-09-22  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* config/mips/mips.h (ISA_HAS_BADDU): New macro.
+	* config/mips/mips.md (*baddu_si_eb, *baddu_si_el,
+	*baddu_di<mode>): New patterns.
+
 2008-09-22  Richard Guenther  <rguenther@suse.de>
 
 	PR tree-optimization/37145
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index ab24869..02a8787 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1010,6 +1010,9 @@ enum mips_code_readable_setting {
    ? TARGET_LLSC && !TARGET_MIPS16	\
    : ISA_HAS_LL_SC)
 
+/* ISA includes the baddu instruction.  */
+#define ISA_HAS_BADDU		TARGET_OCTEON
+
 /* ISA includes the bbit* instructions.  */
 #define ISA_HAS_BBIT		TARGET_OCTEON
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 58d1fd6..f3fdaea 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1188,6 +1188,38 @@
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")
    (set_attr "extended_mips16" "yes")])
+
+;; Combiner patterns for unsigned byte-add.
+
+(define_insn "*baddu_si_eb"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (zero_extend:SI
+	 (subreg:QI
+	  (plus:SI (match_operand:SI 1 "register_operand" "d")
+		   (match_operand:SI 2 "register_operand" "d")) 3)))]
+  "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
+  "baddu\\t%0,%1,%2"
+  [(set_attr "type" "arith")])
+
+(define_insn "*baddu_si_el"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (zero_extend:SI
+	 (subreg:QI
+	  (plus:SI (match_operand:SI 1 "register_operand" "d")
+		   (match_operand:SI 2 "register_operand" "d")) 0)))]
+  "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
+  "baddu\\t%0,%1,%2"
+  [(set_attr "type" "arith")])
+
+(define_insn "*baddu_di<mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=d")
+        (zero_extend:GPR
+	 (truncate:QI
+	  (plus:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:DI 2 "register_operand" "d")))))]
+  "ISA_HAS_BADDU && TARGET_64BIT"
+  "baddu\\t%0,%1,%2"
+  [(set_attr "type" "arith")])
 
 ;;
 ;;  ....................
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 53aacae..89851e5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2008-09-22  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* gcc.target/mips/octeon-baddu-1.c: New test.
+
 2008-09-22  David Edelsohn  <edelsohn@gnu.org>
 
 	PR rtl-optimization/33642
diff --git a/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c b/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c
new file mode 100644
index 0000000..97aacc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-O -march=octeon" } */
+/* { dg-final { scan-assembler-times "\tbaddu\t" 4 } } */
+/* { dg-final { scan-assembler-not "\tandi\t" } } */
+
+NOMIPS16 unsigned char
+g (long long a, long long b)
+{
+  return a + b;
+}
+
+NOMIPS16 unsigned long long
+h (unsigned long long a, unsigned long long b)
+{
+  unsigned char c = a + b;
+  return c;
+}
+
+NOMIPS16 long long
+ff (long long a, long long b)
+{
+  unsigned char c = a + b;
+  return c;
+}
+
+NOMIPS16 int
+gg (int a, int b)
+{
+  return (a + b) & 0xff;
+}