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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:16:27 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:16:27 -0700 |
| commit | 73371f6a702f497479ce50bf81695a5721532307 (patch) | |
| tree | 9694087decb3540d80472973453171f7b257c3ee | |
| parent | 18184fdd765d1a8d98b573cd5f1c11284d965451 (diff) | |
| download | gcc-73371f6a702f497479ce50bf81695a5721532307.zip gcc-73371f6a702f497479ce50bf81695a5721532307.tar.gz gcc-73371f6a702f497479ce50bf81695a5721532307.tar.bz2 | |
i386: Emulate MMX mmx_pmovmskb with SSE
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
From-SVN: r271232
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 30 |
2 files changed, 29 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 666c911..3c003fc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,12 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_pmovmskb): Changed to + define_insn_and_split to support SSE emulation. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_<code>v4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_<code>v8qi3): Likewise. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 9885369..cb6da2d 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1788,14 +1788,30 @@ [(set_attr "type" "mmxshft") (set_attr "mode" "DI")]) -(define_insn "mmx_pmovmskb" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] +(define_insn_and_split "mmx_pmovmskb" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x")] UNSPEC_MOVMSK))] - "TARGET_SSE || TARGET_3DNOW_A" - "pmovmskb\t{%1, %0|%0, %1}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + pmovmskb\t{%1, %0|%0, %1} + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(set (match_dup 0) + (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)) + (set (match_dup 0) + (zero_extend:SI (match_dup 2)))] +{ + /* Generate SSE pmovmskb and zero-extend from QImode to SImode. */ + operands[1] = lowpart_subreg (V16QImode, operands[1], + GET_MODE (operands[1])); + operands[2] = lowpart_subreg (QImode, operands[0], + GET_MODE (operands[0])); +} + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "mmxcvt,ssemov") + (set_attr "mode" "DI,TI")]) (define_expand "mmx_maskmovq" [(set (match_operand:V8QI 0 "memory_operand") |