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| author | Richard Earnshaw <rearnsha@arm.com> | 2019-10-18 19:02:05 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2019-10-18 19:02:05 +0000 |
| commit | 717e1281604655ef608931fff028f02d462e78b6 (patch) | |
| tree | b211d4fa7bdacc2ca8c8cbef9e1175d645ed13a9 | |
| parent | 0250355849a16456a8b8e6dce2d2d7874696649e (diff) | |
| download | gcc-717e1281604655ef608931fff028f02d462e78b6.zip gcc-717e1281604655ef608931fff028f02d462e78b6.tar.gz gcc-717e1281604655ef608931fff028f02d462e78b6.tar.bz2 | |
[arm] Rewrite addsi3_carryin_shift_<optab> in canonical form
The add-with-carry operation which involves a shift doesn't match at present
because it isn't matching the canonical form generated by combine. Fixing
this is simply a matter of re-ordering the operands.
* config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands
to match canonical form.
From-SVN: r277167
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7935f1f..cb2abfe 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-10-18 Richard Earnshaw <rearnsha@arm.com> + * config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands + to match canonical form. + +2019-10-18 Richard Earnshaw <rearnsha@arm.com> + * config/arm/arm.md (zero_extend<mode>di2): Convert to define_expand. (extend<mode>di2): Likewise. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4a7a64e..9754a76 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -913,8 +913,8 @@ (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "reg_or_int_operand" "rM")]) - (match_operand:SI 1 "s_register_operand" "r")) - (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))] + (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))) + (match_operand:SI 1 "s_register_operand" "r")))] "TARGET_32BIT" "adc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") |