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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2013-06-06 15:19:44 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2013-06-06 15:19:44 +0000 |
| commit | 66071e103cdaf8535c63a096aab414db51e06c99 (patch) | |
| tree | 551449ae02669f1fdb1f146de1b55e5c3f883395 | |
| parent | 2297c8ce37031624da21ccd1d5482c1981b180f3 (diff) | |
| download | gcc-66071e103cdaf8535c63a096aab414db51e06c99.zip gcc-66071e103cdaf8535c63a096aab414db51e06c99.tar.gz gcc-66071e103cdaf8535c63a096aab414db51e06c99.tar.bz2 | |
arm-fixed.md (add<mode>3,usadd<mode>3,ssadd<mode>3, [...]): Adjust alternatives for arm_restrict_it.
2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm-fixed.md (add<mode>3,usadd<mode>3,ssadd<mode>3,
sub<mode>3, ussub<mode>3, sssub<mode>3, arm_ssatsihi_shift,
arm_usatsihi): Adjust alternatives for arm_restrict_it.
From-SVN: r199739
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm-fixed.md | 38 |
2 files changed, 30 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b14fbe0..0febdb3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + * config/arm/arm-fixed.md (add<mode>3,usadd<mode>3,ssadd<mode>3, + sub<mode>3, ussub<mode>3, sssub<mode>3, arm_ssatsihi_shift, + arm_usatsihi): Adjust alternatives for arm_restrict_it. + +2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + * config/arm/arm-ldmstm.ml: Set "predicable_short_it" to "no" where appropriate. * config/arm/ldmstm.md: Regenerate. diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index 10da396..12bbbaf 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -19,12 +19,13 @@ ;; This file contains ARM instructions that support fixed-point operations. (define_insn "add<mode>3" - [(set (match_operand:FIXED 0 "s_register_operand" "=r") - (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "r") - (match_operand:FIXED 2 "s_register_operand" "r")))] + [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") + (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") + (match_operand:FIXED 2 "s_register_operand" "l,r")))] "TARGET_32BIT" "add%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "yes,no")]) (define_insn "add<mode>3" [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") @@ -32,7 +33,8 @@ (match_operand:ADDSUB 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "sadd<qaddsub_suf>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "usadd<mode>3" [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") @@ -40,7 +42,8 @@ (match_operand:UQADDSUB 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "uqadd<qaddsub_suf>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "ssadd<mode>3" [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") @@ -48,15 +51,17 @@ (match_operand:QADDSUB 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "qadd<qaddsub_suf>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "sub<mode>3" - [(set (match_operand:FIXED 0 "s_register_operand" "=r") - (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "r") - (match_operand:FIXED 2 "s_register_operand" "r")))] + [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") + (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") + (match_operand:FIXED 2 "s_register_operand" "l,r")))] "TARGET_32BIT" "sub%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "yes,no")]) (define_insn "sub<mode>3" [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") @@ -64,7 +69,8 @@ (match_operand:ADDSUB 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "ssub<qaddsub_suf>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "ussub<mode>3" [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") @@ -73,7 +79,8 @@ (match_operand:UQADDSUB 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "uqsub<qaddsub_suf>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "sssub<mode>3" [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") @@ -81,7 +88,8 @@ (match_operand:QADDSUB 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "qsub<qaddsub_suf>%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) ;; Fractional multiplies. @@ -374,6 +382,7 @@ "TARGET_32BIT && arm_arch6" "ssat%?\\t%0, #16, %2%S1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "insn" "sat") (set_attr "shift" "1") (set_attr "type" "alu_shift")]) @@ -384,4 +393,5 @@ "TARGET_INT_SIMD" "usat%?\\t%0, #16, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "insn" "sat")]) |