diff options
| author | Alexander Ivchenko <alexander.ivchenko@intel.com> | 2014-10-14 08:26:09 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2014-10-14 08:26:09 +0000 |
| commit | 5f64b49668022924dcb057e3f262facac7a93a69 (patch) | |
| tree | 3590133ebca85d5a0bdb665685c8c34d3420cf53 | |
| parent | 26358fb6a0c566c2cdca5107ff60d249abfc028b (diff) | |
| download | gcc-5f64b49668022924dcb057e3f262facac7a93a69.zip gcc-5f64b49668022924dcb057e3f262facac7a93a69.tar.gz gcc-5f64b49668022924dcb057e3f262facac7a93a69.tar.bz2 | |
AVX-512. 62/n. Add vpmaddubsw,vdbpsadbw insn patterns.
gcc/
* config/i386/sse.md
(define_c_enum "unspec"): Add UNSPEC_DBPSADBW, UNSPEC_PMADDUBSW512.
(define_insn "avx512bw_pmaddubsw512<mode><mask_name>"): New.
(define_insn "<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>"):
Ditto.
Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r216180
| -rw-r--r-- | gcc/ChangeLog | 15 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 33 |
2 files changed, 48 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5806e05..ff14980 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -8,6 +8,21 @@ Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/i386/sse.md + (define_c_enum "unspec"): Add UNSPEC_DBPSADBW, UNSPEC_PMADDUBSW512. + (define_insn "avx512bw_pmaddubsw512<mode><mask_name>"): New. + (define_insn "<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>"): + Ditto. + +2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com> + Maxim Kuznetsov <maxim.kuznetsov@intel.com> + Anna Tikhonova <anna.tikhonova@intel.com> + Ilya Tocar <ilya.tocar@intel.com> + Andrey Turetskiy <andrey.turetskiy@intel.com> + Ilya Verbin <ilya.verbin@intel.com> + Kirill Yukhin <kirill.yukhin@intel.com> + Michael Zolotukhin <michael.v.zolotukhin@intel.com> + + * config/i386/sse.md (define_insn "<sse>_andnot<VF_128_256:mode>3<mask_name>"): Add masking, use VF_128_256 mode iterator and update assembler emit code. (define_insn "<sse>_andnot<VF_512:mode>3<mask_name>"): New. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a760f53..a71f969 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -130,6 +130,8 @@ UNSPEC_SHA256RNDS2 ;; For AVX512BW support + UNSPEC_DBPSADBW + UNSPEC_PMADDUBSW512 UNSPEC_PSHUFHW UNSPEC_PSHUFLW @@ -13236,6 +13238,20 @@ (set_attr "prefix" "vex") (set_attr "mode" "OI")]) +;; The correct representation for this is absolutely enormous, and +;; surely not generally useful. +(define_insn "avx512bw_pmaddubsw512<mode><mask_name>" + [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") + (unspec:VI2_AVX512VL + [(match_operand:<dbpsadbwmode> 1 "register_operand" "v") + (match_operand:<dbpsadbwmode> 2 "nonimmediate_operand" "vm")] + UNSPEC_PMADDUBSW512))] + "TARGET_AVX512BW" + "vpmaddubsw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"; + [(set_attr "type" "sseiadd") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + (define_insn "ssse3_pmaddubsw128" [(set (match_operand:V8HI 0 "register_operand" "=x,x") (ss_plus:V8HI @@ -17902,6 +17918,23 @@ [(set_attr "prefix" "evex") (set_attr "mode" "<ssescalarmode>")]) +;; The correct representation for this is absolutely enormous, and +;; surely not generally useful. +(define_insn "<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>" + [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") + (unspec:VI2_AVX512VL + [(match_operand:<dbpsadbwmode> 1 "register_operand" "v") + (match_operand:<dbpsadbwmode> 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_operand")] + UNSPEC_DBPSADBW))] + "TARGET_AVX512BW" + "vdbpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}" + [(set_attr "isa" "avx") + (set_attr "type" "sselog1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + (define_insn "clz<mode>2<mask_name>" [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") (clz:VI48_AVX512VL |