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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:08:38 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:08:38 -0700 |
| commit | 5d48867be5b9fa92d3c171418eb5d46f2ad6d640 (patch) | |
| tree | 225f5d9da0373c5a46fb5a8e5009a8ae5eff5dc1 | |
| parent | d0e9bf2a6db4df95b776c5bcd728f0e159116659 (diff) | |
| download | gcc-5d48867be5b9fa92d3c171418eb5d46f2ad6d640.zip gcc-5d48867be5b9fa92d3c171418eb5d46f2ad6d640.tar.gz gcc-5d48867be5b9fa92d3c171418eb5d46f2ad6d640.tar.bz2 | |
i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE
Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE. Only SSE register
source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_ashr<mode>3): Also allow
TARGET_MMX_WITH_SSE. Add SSE emulation.
(mmx_<shift_insn><mode>3): Likewise.
(ashr<mode>3): New.
(<shift_insn><mode>3): Likewise.
From-SVN: r271221
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 50 |
2 files changed, 45 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 597ba81..ecf9f7b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,15 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_ashr<mode>3): Also allow + TARGET_MMX_WITH_SSE. Add SSE emulation. + (mmx_<shift_insn><mode>3): Likewise. + (ashr<mode>3): New. + (<shift_insn><mode>3): Likewise. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 7cbca96..73110b5 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -984,32 +984,54 @@ (set_attr "mode" "DI")]) (define_insn "mmx_ashr<mode>3" - [(set (match_operand:MMXMODE24 0 "register_operand" "=y") + [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv") (ashiftrt:MMXMODE24 - (match_operand:MMXMODE24 1 "register_operand" "0") - (match_operand:DI 2 "nonmemory_operand" "yN")))] - "TARGET_MMX" - "psra<mmxvecsize>\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") + (match_operand:MMXMODE24 1 "register_operand" "0,0,Yv") + (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + psra<mmxvecsize>\t{%2, %0|%0, %2} + psra<mmxvecsize>\t{%2, %0|%0, %2} + vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sseishft,sseishft") (set (attr "length_immediate") (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) + +(define_expand "ashr<mode>3" + [(set (match_operand:MMXMODE24 0 "register_operand") + (ashiftrt:MMXMODE24 + (match_operand:MMXMODE24 1 "register_operand") + (match_operand:DI 2 "nonmemory_operand")))] + "TARGET_MMX_WITH_SSE") (define_insn "mmx_<shift_insn><mode>3" - [(set (match_operand:MMXMODE248 0 "register_operand" "=y") + [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv") (any_lshift:MMXMODE248 - (match_operand:MMXMODE248 1 "register_operand" "0") - (match_operand:DI 2 "nonmemory_operand" "yN")))] - "TARGET_MMX" - "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") + (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv") + (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + p<vshift><mmxvecsize>\t{%2, %0|%0, %2} + p<vshift><mmxvecsize>\t{%2, %0|%0, %2} + vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sseishft,sseishft") (set (attr "length_immediate") (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) + +(define_expand "<shift_insn><mode>3" + [(set (match_operand:MMXMODE248 0 "register_operand") + (any_lshift:MMXMODE248 + (match_operand:MMXMODE248 1 "register_operand") + (match_operand:DI 2 "nonmemory_operand")))] + "TARGET_MMX_WITH_SSE") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; |