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| author | liuhongt <hongtao.liu@intel.com> | 2020-08-26 15:24:10 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2020-08-28 15:45:00 +0800 |
| commit | 58d6eea0e0754351b399a4b85562f81326a184ad (patch) | |
| tree | 8219043e1921967f14659e8d02b1d1dd8e5b6ebb | |
| parent | 6ba09730375b47c0442b3638d02d75fb3430425c (diff) | |
| download | gcc-58d6eea0e0754351b399a4b85562f81326a184ad.zip gcc-58d6eea0e0754351b399a4b85562f81326a184ad.tar.gz gcc-58d6eea0e0754351b399a4b85562f81326a184ad.tar.bz2 | |
Add expander for movp2hi and movp2qi.
2020-08-30 Uros Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/96744
* config/i386/i386-expand.c (split_double_mode): Also handle
E_P2HImode and E_P2QImode.
* config/i386/sse.md (MASK_DWI): New define_mode_iterator.
(mov<mode>): New expander for P2HI,P2QI.
(*mov<mode>_internal): New define_insn_and_split to split
movement of P2QI/P2HI to 2 movqi/movhi patterns after reload.
gcc/testsuite/ChangeLog:
* gcc.target/i386/double_mask_reg-1.c: New test.
| -rw-r--r-- | gcc/config/i386/i386-expand.c | 6 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 24 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/double_mask_reg-1.c | 19 |
3 files changed, 49 insertions, 0 deletions
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index a284f7e..e6f8b31 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -116,6 +116,12 @@ split_double_mode (machine_mode mode, rtx operands[], case E_DImode: half_mode = SImode; break; + case E_P2HImode: + half_mode = HImode; + break; + case E_P2QImode: + half_mode = QImode; + break; default: gcc_unreachable (); } diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 380dc45..44aa61d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -23463,6 +23463,30 @@ (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")]) +(define_mode_iterator MASK_DWI [P2QI P2HI]) + +(define_expand "mov<mode>" + [(set (match_operand:MASK_DWI 0 "nonimmediate_operand") + (match_operand:MASK_DWI 1 "nonimmediate_operand"))] + "TARGET_AVX512VP2INTERSECT" +{ + if (MEM_P (operands[1]) && MEM_P (operands[2])) + operands[1] = force_reg (<MODE>mode, operands[1]); +}) + +(define_insn_and_split "*mov<mode>_internal" + [(set (match_operand:MASK_DWI 0 "nonimmediate_operand" "=k,o") + (match_operand:MASK_DWI 1 "nonimmediate_operand" "ko,k"))] + "TARGET_AVX512VP2INTERSECT + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3))] +{ + split_double_mode (<MODE>mode, &operands[0], 2, &operands[0], &operands[2]); +}) + (define_insn "avx512vp2intersect_2intersect<mode>" [(set (match_operand:P2QI 0 "register_operand" "=k") (unspec:P2QI diff --git a/gcc/testsuite/gcc.target/i386/double_mask_reg-1.c b/gcc/testsuite/gcc.target/i386/double_mask_reg-1.c new file mode 100644 index 0000000..79ba1ce --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/double_mask_reg-1.c @@ -0,0 +1,19 @@ +/* PR target/96744 */ +/* { dg-do compile } */ +/* { dg-options "-mavx512vp2intersect -O2" } */ + +#include<immintrin.h> +void +_mm512_2intersect_epi64_cut (__m512i __A, __m512i __B, __mmask8 *__U, + __mmask8 *__M) +{ + __builtin_ia32_2intersectq512 (__U, __M, (__v8di) __A, (__v8di) __B); +} + +void +_mm512_2intersect_epi32_cut (__m512i __A, __m512i __B, __mmask16 *__U, + __mmask16 *__M) +{ + __builtin_ia32_2intersectd512 (__U, __M, (__v16si) __A, (__v16si) __B); +} + |