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authorAlan Modra <amodra@bigpond.net.au>2002-02-23 02:11:07 +0000
committerDavid Edelsohn <dje@gcc.gnu.org>2002-02-22 21:11:07 -0500
commit57deb3a13bdb2f425f51b274d3369aaeca79e184 (patch)
tree885fc13cb45924174bf780d8d76a1f25b284a750
parente72247f417055c24de8e8ceb755b02f03222718c (diff)
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- Add missing mask_operand patch.
From-SVN: r49984
-rw-r--r--gcc/ChangeLog1
-rw-r--r--gcc/config/rs6000/rs6000.c5
2 files changed, 6 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 218f811..4be4f46 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -9,6 +9,7 @@
Simplify comparison of `low'.
(add_operand): Fix formatting.
(non_add_cint_operand): Use CONST_OK_FOR_LETTER_P.
+ (mask_operand): Disallow mask to wrap in 64-bit mode.
(rs6000_stack_info): Remove redundant test setting push_p.
(output_toc): Fix formatting.
* config/rs6000/rs6000.md (boolsi3, boolcsi3 splitters): Use
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 863126e..70adbf8 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1399,6 +1399,11 @@ mask_operand (op, mode)
c = INTVAL (op);
+ /* Fail in 64-bit mode if the mask wraps around because the upper
+ 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
+ if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
+ return 0;
+
/* We don't change the number of transitions by inverting,
so make sure we start with the LS bit zero. */
if (c & 1)