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| author | Alan Lawrence <alan.lawrence@arm.com> | 2014-12-19 17:44:36 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2014-12-19 17:44:36 +0000 |
| commit | 4f2962fd47452bfe0d343392f6417c08fa221083 (patch) | |
| tree | e88e33cdc49b13c2cfe2326035239e822f1b827a | |
| parent | fc2770b996c502dfa71980b7f3a4e2b0cf688275 (diff) | |
| download | gcc-4f2962fd47452bfe0d343392f6417c08fa221083.zip gcc-4f2962fd47452bfe0d343392f6417c08fa221083.tar.gz gcc-4f2962fd47452bfe0d343392f6417c08fa221083.tar.bz2 | |
[AArch64 1/3] Don't disparage add/sub in SIMD registers
* config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize
SIMD reg variant.
From-SVN: r218958
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 |
2 files changed, 11 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 19b33e7..f27d698 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-12-19 Alan Lawrence <alan.lawrence@arm.com> + + * config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize + SIMD reg variant. + 2014-12-19 Martin Liska <mliska@suse.cz> PR ipa/63569 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 12532c1..3e84346 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1434,10 +1434,10 @@ (define_insn "*adddi3_aarch64" [(set - (match_operand:DI 0 "register_operand" "=rk,rk,rk,!w") + (match_operand:DI 0 "register_operand" "=rk,rk,rk,w") (plus:DI - (match_operand:DI 1 "register_operand" "%rk,rk,rk,!w") - (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,!w")))] + (match_operand:DI 1 "register_operand" "%rk,rk,rk,w") + (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,w")))] "" "@ add\\t%x0, %x1, %2 @@ -1908,9 +1908,9 @@ ) (define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=rk,!w") - (minus:DI (match_operand:DI 1 "register_operand" "r,!w") - (match_operand:DI 2 "register_operand" "r,!w")))] + [(set (match_operand:DI 0 "register_operand" "=rk,w") + (minus:DI (match_operand:DI 1 "register_operand" "r,w") + (match_operand:DI 2 "register_operand" "r,w")))] "" "@ sub\\t%x0, %x1, %x2 |