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| author | Jie Zhang <jie@codesourcery.com> | 2010-07-03 16:35:02 +0000 |
|---|---|---|
| committer | Jie Zhang <jiez@gcc.gnu.org> | 2010-07-03 16:35:02 +0000 |
| commit | 4e6f5666ac37c9cb8cc86008c906b0095b628ac4 (patch) | |
| tree | c6a8034b7dc81dc63de262449fe660e1b939ede7 | |
| parent | 6687b74039b24bf8e3bdd35c4f250d5e08e5d5a3 (diff) | |
| download | gcc-4e6f5666ac37c9cb8cc86008c906b0095b628ac4.zip gcc-4e6f5666ac37c9cb8cc86008c906b0095b628ac4.tar.gz gcc-4e6f5666ac37c9cb8cc86008c906b0095b628ac4.tar.bz2 | |
vfp.md (*push_multi_vfp): Use vfp_register_operand as predicate for operand 1 and remove its constraint.
* config/arm/vfp.md (*push_multi_vfp): Use vfp_register_operand
as predicate for operand 1 and remove its constraint.
* config/arm/predicates.md (vfp_register_operand): New.
* config/arm/arm.md (*push_multi): Remove the constraint of
operand 1.
(*push_fp_multi): Likewise.
From-SVN: r161775
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 4 | ||||
| -rw-r--r-- | gcc/config/arm/predicates.md | 15 | ||||
| -rw-r--r-- | gcc/config/arm/vfp.md | 2 |
4 files changed, 27 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8ef121a..8aceaf7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2010-07-03 Jie Zhang <jie@codesourcery.com> + + * config/arm/vfp.md (*push_multi_vfp): Use vfp_register_operand + as predicate for operand 1 and remove its constraint. + * config/arm/predicates.md (vfp_register_operand): New. + * config/arm/arm.md (*push_multi): Remove the constraint of + operand 1. + (*push_fp_multi): Likewise. + 2010-07-03 Eric Botcazou <ebotcazou@adacore.com> * gimplify.c (mostly_copy_tree_r): Deal with BIND_EXPR. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index bf91918..9052bff 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10902,7 +10902,7 @@ (define_insn "*push_multi" [(match_parallel 2 "multi_register_push" [(set (match_operand:BLK 0 "memory_operand" "=m") - (unspec:BLK [(match_operand:SI 1 "s_register_operand" "r")] + (unspec:BLK [(match_operand:SI 1 "s_register_operand" "")] UNSPEC_PUSH_MULT))])] "TARGET_32BIT" "* @@ -10955,7 +10955,7 @@ (define_insn "*push_fp_multi" [(match_parallel 2 "multi_register_push" [(set (match_operand:BLK 0 "memory_operand" "=m") - (unspec:BLK [(match_operand:XF 1 "f_register_operand" "f")] + (unspec:BLK [(match_operand:XF 1 "f_register_operand" "")] UNSPEC_PUSH_MULT))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "* diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 0ff7aef..f53c54f 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -73,6 +73,21 @@ || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); }) +(define_predicate "vfp_register_operand" + (match_code "reg,subreg") +{ + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + /* We don't consider registers whose class is NO_REGS + to be a register operand. */ + return (GET_CODE (op) == REG + && (REGNO (op) >= FIRST_PSEUDO_REGISTER + || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS + || (TARGET_VFPD32 + && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); +}) + (define_special_predicate "subreg_lowpart_operator" (and (match_code "subreg") (match_test "subreg_lowpart_p (op)"))) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 02d527b..26fd118 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1132,7 +1132,7 @@ (define_insn "*push_multi_vfp" [(match_parallel 2 "multi_register_push" [(set (match_operand:BLK 0 "memory_operand" "=m") - (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")] + (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")] UNSPEC_PUSH_MULT))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "* return vfp_output_fstmd (operands);" |