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author | Tamar Christina <tamar.christina@arm.com> | 2017-10-26 09:59:14 +0000 |
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committer | Tamar Christina <tnfchris@gcc.gnu.org> | 2017-10-26 09:59:14 +0000 |
commit | 4bc19a3b1a9fe74e515b7c54082bbad27decc227 (patch) | |
tree | fccd162b487cb35de75147c318253bf927386a8d | |
parent | 2b5de01437baf9417c4e7d0831037ed09a0557d5 (diff) | |
download | gcc-4bc19a3b1a9fe74e515b7c54082bbad27decc227.zip gcc-4bc19a3b1a9fe74e515b7c54082bbad27decc227.tar.gz gcc-4bc19a3b1a9fe74e515b7c54082bbad27decc227.tar.bz2 |
2017-10-26 Tamar Christina <tamar.christina@arm.com>
* gcc.dg/vect/vect-reduc-dot-s8a.c
(dg-additional-options, dg-require-effective-target): Add +dotprod.
* gcc.dg/vect/vect-reduc-dot-u8a.c
(dg-additional-options, dg-require-effective-target): Add +dotprod.
From-SVN: r254101
-rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8a.c | 3 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-reduc-dot-u8a.c | 3 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/simd/vdot-exec.c | 55 |
4 files changed, 68 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6d42152..d71ab16 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,12 @@ 2017-10-26 Tamar Christina <tamar.christina@arm.com> + * gcc.dg/vect/vect-reduc-dot-s8a.c + (dg-additional-options, dg-require-effective-target): Add +dotprod. + * gcc.dg/vect/vect-reduc-dot-u8a.c + (dg-additional-options, dg-require-effective-target): Add +dotprod. + +2017-10-26 Tamar Christina <tamar.christina@arm.com> + * lib/target-supports.exp (check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache): New. (check_effective_target_arm_v8_2a_dotprod_neon_ok): New. diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8a.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8a.c index dc4f520..ac67474 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8a.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8a.c @@ -1,4 +1,7 @@ /* { dg-require-effective-target vect_int } */ +/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw { target { aarch64*-*-* || arm*-*-* } } } */ +/* { dg-additional-options "-march=armv8.2-a+dotprod" { target { aarch64*-*-* } } } */ +/* { dg-add-options arm_v8_2a_dotprod_neon } */ #include <stdarg.h> #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-u8a.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-u8a.c index f3cc6c7..d020f64 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-u8a.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-u8a.c @@ -1,4 +1,7 @@ /* { dg-require-effective-target vect_int } */ +/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw { target { aarch64*-*-* || arm*-*-* } } } */ +/* { dg-additional-options "-march=armv8.2-a+dotprod" { target { aarch64*-*-* } } } */ +/* { dg-add-options arm_v8_2a_dotprod_neon } */ #include <stdarg.h> #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.target/arm/simd/vdot-exec.c b/gcc/testsuite/gcc.target/arm/simd/vdot-exec.c new file mode 100644 index 0000000..054f470 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vdot-exec.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-additional-options "-O3" } */ +/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw } */ +/* { dg-add-options arm_v8_2a_dotprod_neon } */ + +#include <arm_neon.h> + +extern void abort(); + +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +# define ORDER(x, y) y +#else +# define ORDER(x, y) x - y +#endif + +#define P(n1,n2) n1,n1,n1,n1,n2,n2,n2,n2 +#define ARR(nm, p, ty, ...) ty nm##_##p = { __VA_ARGS__ } +#define TEST(t1, t2, t3, f, r1, r2, n1, n2) \ + ARR(f, x, t1, r1); \ + ARR(f, y, t2, r2); \ + t3 f##_##r = {0}; \ + f##_##r = f (f##_##r, f##_##x, f##_##y); \ + if (f##_##r[0] != n1 || f##_##r[1] != n2) \ + abort (); + +#define TEST_LANE(t1, t2, t3, f, r1, r2, n1, n2, n3, n4) \ + ARR(f, x, t1, r1); \ + ARR(f, y, t2, r2); \ + t3 f##_##rx = {0}; \ + f##_##rx = f (f##_##rx, f##_##x, f##_##y, ORDER (1, 0)); \ + if (f##_##rx[0] != n1 || f##_##rx[1] != n2) \ + abort (); \ + t3 f##_##rx1 = {0}; \ + f##_##rx1 = f (f##_##rx1, f##_##x, f##_##y, ORDER (1, 1)); \ + if (f##_##rx1[0] != n3 || f##_##rx1[1] != n4) \ + abort (); \ + +int +main() +{ + TEST (uint8x8_t, uint8x8_t, uint32x2_t, vdot_u32, P(1,2), P(2,3), 8, 24); + TEST (int8x8_t, int8x8_t, int32x2_t, vdot_s32, P(1,2), P(-2,-3), -8, -24); + + TEST (uint8x16_t, uint8x16_t, uint32x4_t, vdotq_u32, P(1,2), P(2,3), 8, 24); + TEST (int8x16_t, int8x16_t, int32x4_t, vdotq_s32, P(1,2), P(-2,-3), -8, -24); + + TEST_LANE (uint8x8_t, uint8x8_t, uint32x2_t, vdot_lane_u32, P(1,2), P(2,3), 8, 16, 12, 24); + + TEST_LANE (int8x8_t, int8x8_t, int32x2_t, vdot_lane_s32, P(1,2), P(-2,-3), -8, -16, -12, -24); + + TEST_LANE (uint8x16_t, uint8x8_t, uint32x4_t, vdotq_lane_u32, P(1,2), P(2,3), 8, 16, 12, 24); + TEST_LANE (int8x16_t, int8x8_t, int32x4_t, vdotq_lane_s32, P(1,2), P(-2,-3), -8, -16, -12, -24); + + return 0; +} |