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| author | Andrey Belevantsev <abel@ispras.ru> | 2019-04-01 21:05:08 +0300 |
|---|---|---|
| committer | Alexander Monakov <amonakov@gcc.gnu.org> | 2019-04-01 21:05:08 +0300 |
| commit | 4b52560099c1b744a0e639daea4805fe10fb3219 (patch) | |
| tree | 6fb365fd3a34328afb00b2fd67c67e9f56cf9595 | |
| parent | 5ed22cbbfce94c6fca8e4247a74315aacb759918 (diff) | |
| download | gcc-4b52560099c1b744a0e639daea4805fe10fb3219.zip gcc-4b52560099c1b744a0e639daea4805fe10fb3219.tar.gz gcc-4b52560099c1b744a0e639daea4805fe10fb3219.tar.bz2 | |
sel-sched: correct reset of reset_sched_cycles_p (PR 85412)
2019-04-01 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/85412
* sel-sched.c (sel_sched_region): Assign reset_sched_cycles_p before
sel_sched_region_1, not after.
* gcc.dg/pr85412.c: New test.
From-SVN: r270065
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/sel-sched.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr85412.c | 21 |
4 files changed, 33 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9afd09b..7b745c6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2019-04-01 Andrey Belevantsev <abel@ispras.ru> + PR rtl-optimization/85412 + * sel-sched.c (sel_sched_region): Assign reset_sched_cycles_p before + sel_sched_region_1, not after. + +2019-04-01 Andrey Belevantsev <abel@ispras.ru> + PR rtl-optimization/86928 * sel-sched-ir.c (sel_redirect_edge_and_branch_force): Invoke compute_live if necessary. diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c index 338d7c0..552dd0b 100644 --- a/gcc/sel-sched.c +++ b/gcc/sel-sched.c @@ -7650,11 +7650,11 @@ sel_sched_region (int rgn) /* Schedule always selecting the next insn to make the correct data for bundling or other later passes. */ pipelining_p = false; + reset_sched_cycles_p = false; force_next_insn = 1; sel_sched_region_1 (); force_next_insn = 0; } - reset_sched_cycles_p = pipelining_p; sel_region_finish (reset_sched_cycles_p); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 244ae87..39e3934 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-04-01 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/85412 + * gcc.dg/pr85412.c: New test. + 2019-04-01 Paolo Carlini <paolo.carlini@oracle.com> PR c++/62207 diff --git a/gcc/testsuite/gcc.dg/pr85412.c b/gcc/testsuite/gcc.dg/pr85412.c new file mode 100644 index 0000000..11b8cec --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr85412.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-O1 -fpeephole2 -fschedule-insns2 -fsel-sched-pipelining -fselective-scheduling2 -ftree-loop-if-convert -fno-if-conversion -fno-move-loop-invariants -fno-split-wide-types -fno-tree-dominator-opts" } */ +/* { dg-additional-options "-march=bonnell" { target x86_64-*-* } } */ + +__int128 jv; + +void +zm (__int128 g9, unsigned short int sm, short int hk) +{ + while (hk < 1) + { + if (jv == 0) + sm *= g9; + + if (sm < jv) + hk = sm; + + g9 |= sm == hk; + } +} |