diff options
| author | Richard Sandiford <rdsandiford@googlemail.com> | 2014-01-08 19:32:56 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2014-01-08 19:32:56 +0000 |
| commit | 3f140f3291e6fdc0a85a1e1efd4c79643f3ed22f (patch) | |
| tree | 745ac9ea0a684cf5bd4d27b067d4441b8f97c798 | |
| parent | f585f02f977fc342e45853d2d1789c710399a24e (diff) | |
| download | gcc-3f140f3291e6fdc0a85a1e1efd4c79643f3ed22f.zip gcc-3f140f3291e6fdc0a85a1e1efd4c79643f3ed22f.tar.gz gcc-3f140f3291e6fdc0a85a1e1efd4c79643f3ed22f.tar.bz2 | |
revert: mips.c (mips_truncated_op_cost): New function.
gcc/
Revert:
2012-10-07 Richard Sandiford <rdsandiford@googlemail.com>
* config/mips/mips.c (mips_truncated_op_cost): New function.
(mips_rtx_costs): Adjust test for BADDU.
* config/mips/mips.md (*baddu_di<mode>): Push truncates to operands.
2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>
* config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...
(*baddu_si): ...this new pattern.
From-SVN: r206440
| -rw-r--r-- | gcc/ChangeLog | 14 | ||||
| -rw-r--r-- | gcc/config/mips/mips.c | 20 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 24 |
3 files changed, 36 insertions, 22 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 89aa400..ff81a81 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2014-01-08 Richard Sandiford <rdsandiford@googlemail.com> + + Revert: + 2012-10-07 Richard Sandiford <rdsandiford@googlemail.com> + + * config/mips/mips.c (mips_truncated_op_cost): New function. + (mips_rtx_costs): Adjust test for BADDU. + * config/mips/mips.md (*baddu_di<mode>): Push truncates to operands. + + 2012-10-02 Richard Sandiford <rdsandiford@googlemail.com> + + * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into... + (*baddu_si): ...this new pattern. + 2014-01-08 Jakub Jelinek <jakub@redhat.com> PR ipa/59722 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index aa1a5ea..617391c 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -3634,17 +3634,6 @@ mips_set_reg_reg_cost (enum machine_mode mode) } } -/* Return the cost of an operand X that can be trucated for free. - SPEED says whether we're optimizing for size or speed. */ - -static int -mips_truncated_op_cost (rtx x, bool speed) -{ - if (GET_CODE (x) == TRUNCATE) - x = XEXP (x, 0); - return set_src_cost (x, speed); -} - /* Implement TARGET_RTX_COSTS. */ static bool @@ -4037,13 +4026,12 @@ mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, case ZERO_EXTEND: if (outer_code == SET && ISA_HAS_BADDU + && (GET_CODE (XEXP (x, 0)) == TRUNCATE + || GET_CODE (XEXP (x, 0)) == SUBREG) && GET_MODE (XEXP (x, 0)) == QImode - && GET_CODE (XEXP (x, 0)) == PLUS) + && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) { - rtx plus = XEXP (x, 0); - *total = (COSTS_N_INSNS (1) - + mips_truncated_op_cost (XEXP (plus, 0), speed) - + mips_truncated_op_cost (XEXP (plus, 1), speed)); + *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed); return true; } *total = mips_zero_extend_cost (mode, XEXP (x, 0)); diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4b0e3b6..813413ee 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1312,20 +1312,32 @@ ;; Combiner patterns for unsigned byte-add. -(define_insn "*baddu_si" +(define_insn "*baddu_si_eb" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI - (plus:QI (match_operand:QI 1 "register_operand" "d") - (match_operand:QI 2 "register_operand" "d"))))] - "ISA_HAS_BADDU" + (subreg:QI + (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) 3)))] + "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" + "baddu\\t%0,%1,%2" + [(set_attr "alu_type" "add")]) + +(define_insn "*baddu_si_el" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI + (subreg:QI + (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) 0)))] + "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) (define_insn "*baddu_di<mode>" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extend:GPR - (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d")) - (truncate:QI (match_operand:DI 2 "register_operand" "d")))))] + (truncate:QI + (plus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))))] "ISA_HAS_BADDU && TARGET_64BIT" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) |