diff options
| author | James E Wilson <wilson@specifixinc.com> | 2005-10-07 17:39:09 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2005-10-07 17:39:09 -0700 |
| commit | 3dbb4dcecd9a93e308c01ec61a725b9a3c9d2381 (patch) | |
| tree | 080c383566f254b0a6a5d13455a71d59d47eb972 | |
| parent | 4383bf26c3af818be23458d7f47e66bb12ee2523 (diff) | |
| download | gcc-3dbb4dcecd9a93e308c01ec61a725b9a3c9d2381.zip gcc-3dbb4dcecd9a93e308c01ec61a725b9a3c9d2381.tar.gz gcc-3dbb4dcecd9a93e308c01ec61a725b9a3c9d2381.tar.bz2 | |
Fix gcc.dg/vect/vect-shift-1.c failure.
* config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use
DImode not VECINT24 for operand 2.
From-SVN: r105113
| -rw-r--r-- | gcc/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/config/ia64/vect.md | 6 |
2 files changed, 6 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a160294..86ba1b2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2005-10-07 James E. Wilson <wilson@specifix.com> + * config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use + DImode not VECINT24 for operand 2. + PR target/23644 * doc/invoke.texi (IA-64 Options, item -mtune): Renamed from -mtune-arch. diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md index 3d4669b..94380bf 100644 --- a/gcc/config/ia64/vect.md +++ b/gcc/config/ia64/vect.md @@ -318,7 +318,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (ashift:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshl<vecsize> %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) @@ -327,7 +327,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (ashiftrt:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshr<vecsize> %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) @@ -336,7 +336,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (lshiftrt:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshr<vecsize>.u %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) |