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| author | David Edelsohn <edelsohn@gnu.org> | 2004-12-11 17:37:25 +0000 |
|---|---|---|
| committer | David Edelsohn <dje@gcc.gnu.org> | 2004-12-11 12:37:25 -0500 |
| commit | 343f6bbf97b13bba5cb6cbd6bdd2bbc601f342c6 (patch) | |
| tree | ce58e675bcb9e263056532c0fccf952149a8dc78 | |
| parent | 3bb18f492119d3ea6a326eb6a3b50ecc4557270b (diff) | |
| download | gcc-343f6bbf97b13bba5cb6cbd6bdd2bbc601f342c6.zip gcc-343f6bbf97b13bba5cb6cbd6bdd2bbc601f342c6.tar.gz gcc-343f6bbf97b13bba5cb6cbd6bdd2bbc601f342c6.tar.bz2 | |
re PR middle-end/18641 (Another ICE caused by reload of a pseudo reg into f0 for a DImode expr)
2004-12-11 David Edelsohn <edelsohn@gnu.org>
Ulrich Weigand <uweigand@de.ibm.com>
PR target/18641
* config/rs6000/darwin.h (PREFERRED_RELOAD_CLASS): Reload all
constants into all register classes intersecting with FLOAT_REGS
via memory.
* config/rs6000/rs6000.h (PREFERRED_RELOAD_CLASS): Same.
* config/rs6000/rs6000.md (movdi_internal32): Ignore FPRs when
choosing register preferences.
(movdi_internal64): Same.
Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com>
From-SVN: r92032
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/rs6000/darwin.h | 4 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 14 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 4 |
4 files changed, 23 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 486ee8d..d4f8a76 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2004-12-11 David Edelsohn <edelsohn@gnu.org> + Ulrich Weigand <uweigand@de.ibm.com> + + PR target/18641 + * config/rs6000/darwin.h (PREFERRED_RELOAD_CLASS): Reload all + constants into all register classes intersecting with FLOAT_REGS + via memory. + * config/rs6000/rs6000.h (PREFERRED_RELOAD_CLASS): Same. + * config/rs6000/rs6000.md (movdi_internal32): Ignore FPRs when + choosing register preferences. + (movdi_internal64): Same. + 2004-12-11 Kazu Hirata <kazu@cs.umass.edu> * tree-into-ssa.c (rewrite_ssa_into_ssa): Free SSA_NAME_AUX diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 3026ae0..51a52ef 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -342,8 +342,8 @@ do { \ #undef PREFERRED_RELOAD_CLASS #define PREFERRED_RELOAD_CLASS(X,CLASS) \ - ((GET_CODE (X) == CONST_DOUBLE \ - && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ + ((CONSTANT_P (X) \ + && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \ ? NO_REGS \ : ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == HIGH) \ && reg_class_subset_p (BASE_REGS, (CLASS))) \ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 5841113..6e74c0e 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1397,13 +1397,13 @@ enum reg_class */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ - (((GET_CODE (X) == CONST_DOUBLE \ - && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ - ? NO_REGS \ - : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ - && (CLASS) == NON_SPECIAL_REGS) \ - ? GENERAL_REGS \ - : (CLASS))) + ((CONSTANT_P (X) \ + && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \ + ? NO_REGS \ + : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ + && (CLASS) == NON_SPECIAL_REGS) \ + ? GENERAL_REGS \ + : (CLASS)) /* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 18d96da..51c4039 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8496,7 +8496,7 @@ ; List r->r after r->"o<>", otherwise reload will try to reload a ; non-offsettable address by using r->r which won't make progress. (define_insn "*movdi_internal32" - [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,f,f,m,r") + [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) @@ -8567,7 +8567,7 @@ }") (define_insn "*movdi_internal64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,??f,f,m,r,*h,*h") + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) |