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| author | Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> | 2013-03-28 17:19:06 +0000 |
|---|---|---|
| committer | Marcus Shawcroft <mshawcroft@gcc.gnu.org> | 2013-03-28 17:19:06 +0000 |
| commit | 2a1d1991eadddddebc75857b72caedcad99cb762 (patch) | |
| tree | 007126a5a87c414f00d64df80e92d942ce3520cf | |
| parent | 7abebba7f231dee68ab5a16f50a3f1b182b5a5cc (diff) | |
| download | gcc-2a1d1991eadddddebc75857b72caedcad99cb762.zip gcc-2a1d1991eadddddebc75857b72caedcad99cb762.tar.gz gcc-2a1d1991eadddddebc75857b72caedcad99cb762.tar.bz2 | |
aarch64.md (*and<mode>3_compare0): New pattern.
2013-03-28 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/aarch64/aarch64.md (*and<mode>3_compare0): New pattern.
(*andsi3_compare0_uxtw): New pattern.
(*and_<SHIFT:optab><mode>3_compare0): New pattern.
(*and_<SHIFT:optab>si3_compare0_uxtw): New pattern.
From-SVN: r197207
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 63 |
2 files changed, 70 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 36ba256..6fc2f47 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2013-03-28 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> + + * config/aarch64/aarch64.md (*and<mode>3_compare0): New pattern. + (*andsi3_compare0_uxtw): New pattern. + (*and_<SHIFT:optab><mode>3_compare0): New pattern. + (*and_<SHIFT:optab>si3_compare0_uxtw): New pattern. + 2013-03-28 Jan Hubicka <jh@suse.cz> * data-streamer-in.c (streamer_read_gcov_count): New function. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c28f4a0..ab73ae3 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2461,6 +2461,69 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "SI")]) +(define_insn "*and<mode>3_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (match_operand:GPI 1 "register_operand" "%r,r") + (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r,r") + (and:GPI (match_dup 1) (match_dup 2)))] + "" + "ands\\t%<w>0, %<w>1, %<w>2" + [(set_attr "v8type" "logics,logics_imm") + (set_attr "mode" "<MODE>")] +) + +;; zero_extend version of above +(define_insn "*andsi3_compare0_uxtw" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:SI (match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "aarch64_logical_operand" "r,K")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] + "" + "ands\\t%w0, %w1, %w2" + [(set_attr "v8type" "logics,logics_imm") + (set_attr "mode" "SI")] +) + +(define_insn "*and_<SHIFT:optab><mode>3_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (SHIFT:GPI + (match_operand:GPI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n")) + (match_operand:GPI 3 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (and:GPI (SHIFT:GPI (match_dup 1) (match_dup 2)) (match_dup 3)))] + "" + "ands\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" + [(set_attr "v8type" "logics_shift") + (set_attr "mode" "<MODE>")] +) + +;; zero_extend version of above +(define_insn "*and_<SHIFT:optab>si3_compare0_uxtw" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:SI (SHIFT:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_si" "n")) + (match_operand:SI 3 "register_operand" "r")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (and:SI (SHIFT:SI (match_dup 1) (match_dup 2)) + (match_dup 3))))] + "" + "ands\\t%w0, %w3, %w1, <SHIFT:shift> %2" + [(set_attr "v8type" "logics_shift") + (set_attr "mode" "SI")] +) + (define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI |