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| author | Jakub Jelinek <jakub@redhat.com> | 2002-05-01 10:27:55 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2002-05-01 10:27:55 +0200 |
| commit | 26aeede49668e5b7da29c670243b7ecca12c7ad4 (patch) | |
| tree | 426779a30e770e0296efa4419af6cd770bc8f452 | |
| parent | 2600218b4da6ad8f4c3160290585430ddd50a5c8 (diff) | |
| download | gcc-26aeede49668e5b7da29c670243b7ecca12c7ad4.zip gcc-26aeede49668e5b7da29c670243b7ecca12c7ad4.tar.gz gcc-26aeede49668e5b7da29c670243b7ecca12c7ad4.tar.bz2 | |
PR target/6512, PR target/5628
PR target/6512, PR target/5628
* config/sparc/sparc.md (movdf_insn_v9only_novis): Don't allow >= %f32
when memory is not aligned.
(movdf_insn_v9only_vis): Likewise.
* config/sparc/sparc.h (SECONDARY_INPUT_RELOAD_CLASS): Request a FP_REGS
temporary for EXTRA_FP_REGS DFmode load from unaligned memory.
(SECONDARY_OUTPUT_RELOAD_CLASS): Similarly.
From-SVN: r52995
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.h | 45 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 8 |
3 files changed, 42 insertions, 21 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ee4572c..39212f4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2002-05-01 Jakub Jelinek <jakub@redhat.com> + + PR target/6512, PR target/5628 + * config/sparc/sparc.md (movdf_insn_v9only_novis): Don't allow >= %f32 + when memory is not aligned. + (movdf_insn_v9only_vis): Likewise. + * config/sparc/sparc.h (SECONDARY_INPUT_RELOAD_CLASS): Request a FP_REGS + temporary for EXTRA_FP_REGS DFmode load from unaligned memory. + (SECONDARY_OUTPUT_RELOAD_CLASS): Similarly. + 2002-05-01 Aldy Hernandez <aldyh@redhat.com> * gcc.dg/altivec-7.c: New. diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index c86eb8f..d70f542 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1423,7 +1423,10 @@ extern const char leaf_reg_remap[]; We need a temporary when loading/storing a HImode/QImode value between memory and the FPU registers. This can happen when combine puts - a paradoxical subreg in a float/fix conversion insn. */ + a paradoxical subreg in a float/fix conversion insn. + + We need a temporary when loading/storing a DFmode value between + unaligned memory and the upper FPU registers. */ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ ((FP_REG_CLASS_P (CLASS) \ @@ -1432,28 +1435,36 @@ extern const char leaf_reg_remap[]; || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ && true_regnum (IN) == -1))) \ ? GENERAL_REGS \ - : (((TARGET_CM_MEDANY \ - && symbolic_operand ((IN), (MODE))) \ - || (TARGET_CM_EMBMEDANY \ - && text_segment_operand ((IN), (MODE)))) \ - && !flag_pic) \ - ? GENERAL_REGS \ - : NO_REGS) + : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ + && GET_CODE (IN) == MEM && TARGET_ARCH32 \ + && ! mem_min_alignment ((IN), 8)) \ + ? FP_REGS \ + : (((TARGET_CM_MEDANY \ + && symbolic_operand ((IN), (MODE))) \ + || (TARGET_CM_EMBMEDANY \ + && text_segment_operand ((IN), (MODE)))) \ + && !flag_pic) \ + ? GENERAL_REGS \ + : NO_REGS) #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ - ((FP_REG_CLASS_P (CLASS) \ + ((FP_REG_CLASS_P (CLASS) \ && ((MODE) == HImode || (MODE) == QImode) \ && (GET_CODE (IN) == MEM \ || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ && true_regnum (IN) == -1))) \ - ? GENERAL_REGS \ - : (((TARGET_CM_MEDANY \ - && symbolic_operand ((IN), (MODE))) \ - || (TARGET_CM_EMBMEDANY \ - && text_segment_operand ((IN), (MODE)))) \ - && !flag_pic) \ - ? GENERAL_REGS \ - : NO_REGS) + ? GENERAL_REGS \ + : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ + && GET_CODE (IN) == MEM && TARGET_ARCH32 \ + && ! mem_min_alignment ((IN), 8)) \ + ? FP_REGS \ + : (((TARGET_CM_MEDANY \ + && symbolic_operand ((IN), (MODE))) \ + || (TARGET_CM_EMBMEDANY \ + && text_segment_operand ((IN), (MODE)))) \ + && !flag_pic) \ + ? GENERAL_REGS \ + : NO_REGS) /* On SPARC it is not possible to directly move data between GENERAL_REGS and FP_REGS. */ diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index db12cfe..8d246d0 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -3535,8 +3535,8 @@ ;; We have available v9 double floats but not 64-bit ;; integer registers and no VIS. (define_insn "*movdf_insn_v9only_novis" - [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,e,*r,o") - (match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGe"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,f,*r,o") + (match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGf"))] "TARGET_FPU && TARGET_V9 && ! TARGET_VIS @@ -3561,8 +3561,8 @@ ;; We have available v9 double floats but not 64-bit ;; integer registers but we have VIS. (define_insn "*movdf_insn_v9only_vis" - [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,e,*r,o") - (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGe"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o") + (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))] "TARGET_FPU && TARGET_VIS && ! TARGET_ARCH64 |