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authorCarl Love <cel@us.ibm.com>2018-05-10 20:22:22 +0000
committerCarl Love <carll@gcc.gnu.org>2018-05-10 20:22:22 +0000
commit267eee04fe4a0f18189f0ab620303656ba316ea7 (patch)
tree386606e65fb044d8b305b66156ffedc5b36db19d
parentb947b54c3d5f50316d88d50decf14879250a9988 (diff)
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rs6000.md (prefetch): Generate ISA 2.06 instructions dcbtt and dcbtstt if operands[2] is 0.
gcc/ChangeLog: 2018-05-10 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000.md (prefetch): Generate ISA 2.06 instructions dcbtt and dcbtstt if operands[2] is 0. From-SVN: r260134
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/rs6000/rs6000.md20
2 files changed, 22 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9b4684c..64ec271 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-05-10 Carl Love <cel@us.ibm.com>
+
+ * config/rs6000/rs6000.md (prefetch): Generate ISA 2.06 instructions
+ dcbtt and dcbtstt if operands[2] is 0.
+
2018-05-10 Uros Bizjak <ubizjak@gmail.com>
PR target/85693
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 26c90b3..253d3f2 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -13166,9 +13166,23 @@
(match_operand:SI 2 "const_int_operand" "n"))]
""
{
- if (GET_CODE (operands[0]) == REG)
- return INTVAL (operands[1]) ? "dcbtst 0,%0" : "dcbt 0,%0";
- return INTVAL (operands[1]) ? "dcbtst %a0" : "dcbt %a0";
+ /* dcbtstt, dcbtt and TM=0b10000 support starts with ISA 2.06. */
+ int inst_select = INTVAL (operands[2]) || !TARGET_POPCNTD;
+
+ if (REG_P (operands[0]))
+ {
+ if (INTVAL (operands[1]) == 0)
+ return inst_select ? "dcbt 0,%0" : "dcbtt 0,%0";
+ else
+ return inst_select ? "dcbtst 0,%0" : "dcbtstt 0,%0";
+ }
+ else
+ {
+ if (INTVAL (operands[1]) == 0)
+ return inst_select ? "dcbt %a0" : "dcbtt %a0";
+ else
+ return inst_select ? "dcbtst %a0" : "dcbtstt %a0";
+ }
}
[(set_attr "type" "load")])