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| author | Richard Henderson <rth@gcc.gnu.org> | 2002-06-10 14:03:33 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2002-06-10 14:03:33 -0700 |
| commit | 21442990fd351ab015ee7a5efba9d6f7e83af2c5 (patch) | |
| tree | df98fc6f89b484b760f03e9721187cb3ecfc2d38 | |
| parent | 158d04aa2886e5b9d77aee79cfa5c9877fac5614 (diff) | |
| download | gcc-21442990fd351ab015ee7a5efba9d6f7e83af2c5.zip gcc-21442990fd351ab015ee7a5efba9d6f7e83af2c5.tar.gz gcc-21442990fd351ab015ee7a5efba9d6f7e83af2c5.tar.bz2 | |
ev5.md: Don't combine shift and mvi insns in one reservation.
* config/alpha/ev5.md: Don't combine shift and mvi insns in one
reservation.
From-SVN: r54453
| -rw-r--r-- | gcc/config/alpha/ev5.md | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/gcc/config/alpha/ev5.md b/gcc/config/alpha/ev5.md index f0dfbdf..69aa4a8 100644 --- a/gcc/config/alpha/ev5.md +++ b/gcc/config/alpha/ev5.md @@ -64,9 +64,14 @@ (eq_attr "type" "jsr")) "ev5_e1") -(define_insn_reservation "ev5_shiftmvi" 2 +(define_insn_reservation "ev5_shift" 1 (and (eq_attr "cpu" "ev5") - (eq_attr "type" "shift,mvi")) + (eq_attr "type" "shift")) + "ev5_e0") + +(define_insn_reservation "ev5_mvi" 2 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "mvi")) "ev5_e0") (define_insn_reservation "ev5_cmov" 2 @@ -119,7 +124,7 @@ ; Model this instead with increased latency on the input instruction. (define_bypass 3 - "ev5_ld,ev5_shiftmvi,ev5_cmov,ev5_iadd,ev5_ilogcmp" + "ev5_ld,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp" "ev5_imull,ev5_imulq,ev5_imulh") (define_bypass 9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh") |