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authorUros Bizjak <ubizjak@gmail.com>2017-04-20 21:04:36 +0200
committerUros Bizjak <uros@gcc.gnu.org>2017-04-20 21:04:36 +0200
commit209173363403d9894743b76cff0d803186ce66a8 (patch)
treefcaa89f2aa91beb01f2a89e1a45d9ce2db821322
parent2414b02252e999ce19e493dbf6f62b1f4186b7b7 (diff)
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re PR target/78090 ([x86_64]: GCC allows integer register for inter unit conversion under -mtune-ctrl=^inter_unit_conversions .)
PR target/78090 * config/i386/constraints.md (Yc): New register constraint. * config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed): Use Yc constraint for alternative 2 of operand 0. Remove preferred_for_speed attribute. testsuite/ChangeLog: PR target/78090 * gcc.target/i386/conversion-2.c: Remove obsolete test. From-SVN: r247036
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/i386/constraints.md5
-rw-r--r--gcc/config/i386/i386.md6
-rw-r--r--gcc/testsuite/ChangeLog5
-rw-r--r--gcc/testsuite/gcc.target/i386/conversion-2.c36
5 files changed, 19 insertions, 41 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d96d987..f4cb919 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2017-04-20 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/78090
+ * config/i386/constraints.md (Yc): New register constraint.
+ * config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed):
+ Use Yc constraint for alternative 2 of operand 0. Remove
+ preferred_for_speed attribute.
+
2017-04-20 Alexander Monakov <amonakov@ispras.ru>
* omp-low.c (lower_lastprivate_clauses): Correct handling of linear and
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index 38d604f..816704f 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -99,6 +99,7 @@
;; We use the Y prefix to denote any number of conditional register sets:
;; z First SSE register.
+;; c SSE inter-unit conversions enabled
;; i SSE2 inter-unit moves to SSE register enabled
;; j SSE2 inter-unit moves from SSE register enabled
;; m MMX inter-unit moves to MMX register enabled
@@ -117,6 +118,10 @@
(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
"First SSE register (@code{%xmm0}).")
+(define_register_constraint "Yc"
+ "TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS"
+ "@internal Any SSE register, when SSE and inter-unit conversions are enabled.")
+
(define_register_constraint "Yi"
"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index d1c3c16..1a902ee 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5207,7 +5207,7 @@
})
(define_insn "*float<SWI48:mode><MODEF:mode>2_mixed"
- [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
+ [(set (match_operand:MODEF 0 "register_operand" "=f,Yc,v")
(float:MODEF
(match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
@@ -5236,10 +5236,6 @@
&& X87_ENABLE_FLOAT (<MODEF:MODE>mode,
<SWI48:MODE>mode)")
]
- (symbol_ref "true")))
- (set (attr "preferred_for_speed")
- (cond [(eq_attr "alternative" "1")
- (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")]
(symbol_ref "true")))])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_i387"
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8c03b6b..b5b5c02 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-04-20 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/78090
+ * gcc.target/i386/conversion-2.c: Remove obsolete test.
+
2017-04-20 David Edelsohn <dje.gcc@gmail.com>
* g++/opt/pr80436.C: XFAIL on AIX.
diff --git a/gcc/testsuite/gcc.target/i386/conversion-2.c b/gcc/testsuite/gcc.target/i386/conversion-2.c
deleted file mode 100644
index cca149a..0000000
--- a/gcc/testsuite/gcc.target/i386/conversion-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -fno-toplevel-reorder -mtune=bdver2" } */
-/* { dg-additional-options "-mregparm=1 -msse -mfpmath=sse" { target ia32 } } */
-
-void __attribute__ ((hot))
-f1 (int x)
-{
- register float f asm ("%xmm0") = x;
- asm volatile ("" :: "x" (f));
-}
-
-void __attribute__ ((cold))
-f2 (int x)
-{
- register float f asm ("%xmm1") = x;
- asm volatile ("" :: "x" (f));
-}
-
-void __attribute__ ((hot))
-f3 (int x)
-{
- register float f asm ("%xmm2") = x;
- asm volatile ("" :: "x" (f));
-}
-
-void __attribute__ ((cold))
-f4 (int x)
-{
- register float f asm ("%xmm3") = x;
- asm volatile ("" :: "x" (f));
-}
-
-/* { dg-final { scan-assembler "sp\\\), %xmm0" } } */
-/* { dg-final { scan-assembler "(ax|di), %xmm1" } } */
-/* { dg-final { scan-assembler "sp\\\), %xmm2" } } */
-/* { dg-final { scan-assembler "(ax|di), %xmm3" } } */