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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:05:48 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:05:48 -0700 |
| commit | 1f0dc22ab5f61ed6b91118f946879dac3e7c9a67 (patch) | |
| tree | 480a8dfe9a9ac059adbbc1c764e4112be0b41033 | |
| parent | 6e9fffcf83638a50cac6e2a127817c409238cfde (diff) | |
| download | gcc-1f0dc22ab5f61ed6b91118f946879dac3e7c9a67.zip gcc-1f0dc22ab5f61ed6b91118f946879dac3e7c9a67.tar.gz gcc-1f0dc22ab5f61ed6b91118f946879dac3e7c9a67.tar.bz2 | |
i386: Emulate MMX plusminus/sat_plusminus with SSE
Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
(plusminus:mmx_<plusminus_insn><mode>3): Check
TARGET_MMX_WITH_SSE.
(sat_plusminus:mmx_<plusminus_insn><mode>3): Likewise.
(<plusminus_insn><mode>3): New.
(*mmx_<plusminus_insn><mode>3): Add SSE emulation.
(*mmx_<plusminus_insn><mode>3): Likewise.
From-SVN: r271217
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 59 |
2 files changed, 49 insertions, 21 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3e5e2d2..3449547 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,17 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI. + (plusminus:mmx_<plusminus_insn><mode>3): Check + TARGET_MMX_WITH_SSE. + (sat_plusminus:mmx_<plusminus_insn><mode>3): Likewise. + (<plusminus_insn><mode>3): New. + (*mmx_<plusminus_insn><mode>3): Add SSE emulation. + (*mmx_<plusminus_insn><mode>3): Likewise. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/i386-expand.c (ix86_split_mmx_punpck): New function. * config/i386/i386-protos.h (ix86_split_mmx_punpck): New prototype. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index b3fc7f3..d0dcd2f 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -45,7 +45,7 @@ ;; 8 byte integral modes handled by MMX (and by extension, SSE) (define_mode_iterator MMXMODEI [V8QI V4HI V2SI]) -(define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI V1DI]) +(define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI (V1DI "TARGET_SSE2")]) ;; All 8-byte vector modes handled by MMX (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF]) @@ -688,39 +688,56 @@ (define_expand "mmx_<plusminus_insn><mode>3" [(set (match_operand:MMXMODEI8 0 "register_operand") (plusminus:MMXMODEI8 - (match_operand:MMXMODEI8 1 "nonimmediate_operand") - (match_operand:MMXMODEI8 2 "nonimmediate_operand")))] - "TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)" + (match_operand:MMXMODEI8 1 "register_mmxmem_operand") + (match_operand:MMXMODEI8 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") + +(define_expand "<plusminus_insn><mode>3" + [(set (match_operand:MMXMODEI 0 "register_operand") + (plusminus:MMXMODEI + (match_operand:MMXMODEI 1 "register_operand") + (match_operand:MMXMODEI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_insn "*mmx_<plusminus_insn><mode>3" - [(set (match_operand:MMXMODEI8 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,Yv") (plusminus:MMXMODEI8 - (match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0") - (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))] - "(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)) + (match_operand:MMXMODEI8 1 "register_mmxmem_operand" "<comm>0,0,Yv") + (match_operand:MMXMODEI8 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "@ + p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2} + p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2} + vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseadd,sseadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_<plusminus_insn><mode>3" [(set (match_operand:MMXMODE12 0 "register_operand") (sat_plusminus:MMXMODE12 - (match_operand:MMXMODE12 1 "nonimmediate_operand") - (match_operand:MMXMODE12 2 "nonimmediate_operand")))] - "TARGET_MMX" + (match_operand:MMXMODE12 1 "register_mmxmem_operand") + (match_operand:MMXMODE12 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_insn "*mmx_<plusminus_insn><mode>3" - [(set (match_operand:MMXMODE12 0 "register_operand" "=y") + [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yv") (sat_plusminus:MMXMODE12 - (match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0") - (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + (match_operand:MMXMODE12 1 "register_mmxmem_operand" "<comm>0,0,Yv") + (match_operand:MMXMODE12 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "@ + p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2} + p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2} + vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseadd,sseadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_mulv4hi3" [(set (match_operand:V4HI 0 "register_operand") |