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| author | Richard Earnshaw <rearnsha@arm.com> | 2002-11-21 14:51:27 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2002-11-21 14:51:27 +0000 |
| commit | 1dda7ee45a250719a8c25828ae5f9b189a2251a2 (patch) | |
| tree | 674094e99d82af2356f168516233b84d6f3a5c11 | |
| parent | e59ff7e93a0fba0df62f6d3aa1904abdddb4dd3e (diff) | |
| download | gcc-1dda7ee45a250719a8c25828ae5f9b189a2251a2.zip gcc-1dda7ee45a250719a8c25828ae5f9b189a2251a2.tar.gz gcc-1dda7ee45a250719a8c25828ae5f9b189a2251a2.tar.bz2 | |
re PR rtl-optimization/2903 ([arm] Optimization bug with long long arithmetic)
PR optimization/2903
* arm.md (anddi_notzesidi_di): Operand 2 is inverted not operand 1.
(anddi_notsesidi_di): Likewise.
From-SVN: r59347
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 6 |
2 files changed, 9 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1e29b8d8..14ea9a2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2002-11-21 Richard Earnshaw <rearnsha@arm.com> + + PR optimization/2903 + * arm.md (anddi_notzesidi_di): Operand 2 is inverted not operand 1. + (anddi_notsesidi_di): Likewise. + 2002-11-21 Kazu Hirata <kazu@cs.umass.edu> * config/h8300/h8300.c (print_operand): Use diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 1d57485..82fafa3 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -2036,7 +2036,7 @@ "TARGET_ARM && reload_completed && operands[0] != operands[1]" - [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) + [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1))) (set (match_dup 3) (match_dup 4))] " { @@ -2053,11 +2053,11 @@ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (not:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) - (match_operand:DI 1 "s_register_operand" "?r,0")))] + (match_operand:DI 1 "s_register_operand" "0,r")))] "TARGET_ARM" "#" "TARGET_ARM && reload_completed" - [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) + [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1))) (set (match_dup 3) (and:SI (not:SI (ashiftrt:SI (match_dup 2) (const_int 31))) (match_dup 4)))] |