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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:15:44 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:15:44 -0700 |
| commit | 18184fdd765d1a8d98b573cd5f1c11284d965451 (patch) | |
| tree | 4eb04b8b357624dbbd29b067436c50fe35834e6b | |
| parent | 42500d835522f0858fb899b17d9b9ffb9efa71d9 (diff) | |
| download | gcc-18184fdd765d1a8d98b573cd5f1c11284d965451.zip gcc-18184fdd765d1a8d98b573cd5f1c11284d965451.tar.gz gcc-18184fdd765d1a8d98b573cd5f1c11284d965451.tar.bz2 | |
i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_<code>v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_<code>v8qi3): Likewise.
(smaxmin:<code>v4hi3): New.
(umaxmin:<code>v8qi3): Likewise.
(smaxmin:*mmx_<code>v4hi3): Add SSE emulation.
(umaxmin:*mmx_<code>v8qi3): Likewise.
From-SVN: r271231
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 68 |
2 files changed, 59 insertions, 20 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 039be8f..666c911 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,17 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_<code>v4hi3): Also check TARGET_MMX + and TARGET_MMX_WITH_SSE. + (mmx_<code>v8qi3): Likewise. + (smaxmin:<code>v4hi3): New. + (umaxmin:<code>v8qi3): Likewise. + (smaxmin:*mmx_<code>v4hi3): Add SSE emulation. + (umaxmin:*mmx_<code>v8qi3): Likewise. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_pinsrw): Add SSE emulation. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 1f4bf1e..9885369 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -948,40 +948,68 @@ (define_expand "mmx_<code>v4hi3" [(set (match_operand:V4HI 0 "register_operand") (smaxmin:V4HI - (match_operand:V4HI 1 "nonimmediate_operand") - (match_operand:V4HI 2 "nonimmediate_operand")))] - "TARGET_SSE || TARGET_3DNOW_A" + (match_operand:V4HI 1 "register_mmxmem_operand") + (match_operand:V4HI 2 "register_mmxmem_operand")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);") + +(define_expand "<code>v4hi3" + [(set (match_operand:V4HI 0 "register_operand") + (smaxmin:V4HI + (match_operand:V4HI 1 "register_operand") + (match_operand:V4HI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);") (define_insn "*mmx_<code>v4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (smaxmin:V4HI - (match_operand:V4HI 1 "nonimmediate_operand" "%0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] - "(TARGET_SSE || TARGET_3DNOW_A) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (<CODE>, V4HImode, operands)" - "p<maxmin_int>w\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "@ + p<maxmin_int>w\t{%2, %0|%0, %2} + p<maxmin_int>w\t{%2, %0|%0, %2} + vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_<code>v8qi3" [(set (match_operand:V8QI 0 "register_operand") (umaxmin:V8QI - (match_operand:V8QI 1 "nonimmediate_operand") - (match_operand:V8QI 2 "nonimmediate_operand")))] - "TARGET_SSE || TARGET_3DNOW_A" + (match_operand:V8QI 1 "register_mmxmem_operand") + (match_operand:V8QI 2 "register_mmxmem_operand")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);") + +(define_expand "<code>v8qi3" + [(set (match_operand:V8QI 0 "register_operand") + (umaxmin:V8QI + (match_operand:V8QI 1 "register_operand") + (match_operand:V8QI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);") (define_insn "*mmx_<code>v8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") (umaxmin:V8QI - (match_operand:V8QI 1 "nonimmediate_operand" "%0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] - "(TARGET_SSE || TARGET_3DNOW_A) + (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (<CODE>, V8QImode, operands)" - "p<maxmin_int>b\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "@ + p<maxmin_int>b\t{%2, %0|%0, %2} + p<maxmin_int>b\t{%2, %0|%0, %2} + vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_ashr<mode>3" [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv") |