diff options
| author | Segher Boessenkool <segher@kernel.crashing.org> | 2019-06-05 01:36:49 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2019-06-05 01:36:49 +0200 |
| commit | 0e9449e69f797c4274f3463e1e10a1796a455e42 (patch) | |
| tree | ac49f61c72c7b4c69b26e770e11626992e46a393 | |
| parent | 1f5aa628e342ab42577273206a67585d04fef5cc (diff) | |
| download | gcc-0e9449e69f797c4274f3463e1e10a1796a455e42.zip gcc-0e9449e69f797c4274f3463e1e10a1796a455e42.tar.gz gcc-0e9449e69f797c4274f3463e1e10a1796a455e42.tar.bz2 | |
rs6000: Add p9kf and p9tf isa values
This adds "p9kf" and "p9tf" isa values, to be used for instruction
alternatives where KFmode resp. TFmode is used.
* config/rs6000/rs6000.md (define_attr "isa"): Add p9kf and p9tf.
(define_attr "enabled"): Handle those new isa values.
From-SVN: r271938
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 10 |
2 files changed, 14 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 857b307..453f017 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/rs6000.md (define_attr "isa"): Add p9kf and p9tf. + (define_attr "enabled"): Handle those new isa values. + +2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/vsx.md (define_mode_attr VSr4): Delete. (define_mode_attr VSr5): Delete. (define_mode_attr VStype_sqrt): Delete. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b8b246a..b1f3bc3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -267,7 +267,7 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v" (const_string "any")) +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? (define_attr "enabled" "" @@ -298,6 +298,14 @@ (and (eq_attr "isa" "p9v") (match_test "TARGET_P9_VECTOR")) (const_int 1) + + (and (eq_attr "isa" "p9kf") + (match_test "TARGET_FLOAT128_TYPE")) + (const_int 1) + + (and (eq_attr "isa" "p9tf") + (match_test "FLOAT128_VECTOR_P (TFmode)")) + (const_int 1) ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor |