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authorMichael Collison <michael.collison@linaro.org>2016-03-03 07:42:02 +0000
committerMichael Collison <collison@gcc.gnu.org>2016-03-03 07:42:02 +0000
commit0a67ef4c4de7bf55d3ef3c7bc61a9480e0d213bd (patch)
treef9fb2bf1fc348a3bac22957e4b32e19598e9a456
parent5147e0e84ef1daf08576c2ebc477b8941f54578f (diff)
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re PR target/70014 ([ARM] Predicate does not match constraint (*subsi3_carryin_const))
2016-03-03 Michael Collison <michael.collison@linaro.org> PR target/70014 * config/arm/arm.md (*subsi3_carryin_const): Change predicate for operand 1 to s_register_operand. Change predicate for operand 2 to arm_not_immediate_operand. From-SVN: r233927
-rw-r--r--gcc/ChangeLog7
-rw-r--r--gcc/config/arm/arm.md4
2 files changed, 9 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4800e1d..f149eba 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-03-03 Michael Collison <michael.collison@linaro.org>
+
+ PR target/70014
+ * config/arm/arm.md (*subsi3_carryin_const): Change predicate
+ for operand 1 to s_register_operand. Change predicate for operand
+ 2 to arm_not_immediate_operand.
+
2016-03-02 H.J. Lu <hongjiu.lu@intel.com>
* doc/tm.texi: Regenerated.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index e67239deb..47171b9 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -883,8 +883,8 @@
(define_insn "*subsi3_carryin_const"
[(set (match_operand:SI 0 "s_register_operand" "=r")
- (minus:SI (plus:SI (match_operand:SI 1 "reg_or_int_operand" "r")
- (match_operand:SI 2 "arm_not_operand" "K"))
+ (minus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "arm_not_immediate_operand" "K"))
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
"TARGET_32BIT"
"sbc\\t%0, %1, #%B2"