h8300.md (stm_h8300s_2): New.

	* config/h8300/h8300.md (stm_h8300s_2): New.
	(stm_h8300s_3): Likewise.
	(stm_h8300s_4): Likewise.
	(five define_peephole2): Likewise.

From-SVN: r59715

2 files changed, 171 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index df0aa95..f09b4db 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
 2002-12-02  Kazu Hirata  <kazu@cs.umass.edu>
 
+	* config/h8300/h8300.md (stm_h8300s_2): New.
+	(stm_h8300s_3): Likewise.
+	(stm_h8300s_4): Likewise.
+	(five define_peephole2): Likewise.
+
+2002-12-02  Kazu Hirata  <kazu@cs.umass.edu>
+
 	* ra-build.c: Fix a comment typo.
 
 2002-12-01  Kazu Hirata  <kazu@cs.umass.edu>
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index c846ac67..8fac7dd 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -1688,6 +1688,68 @@
    (set_attr "length" "2")])
 
 ;; ----------------------------------------------------------------------
+;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_insn "*stm_h8300s_2"
+  [(parallel
+     [(set (reg:SI SP_REG)
+	   (plus:SI (reg:SI SP_REG) (const_int -8)))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
+	   (match_operand:SI 0 "register_operand" ""))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
+	   (match_operand:SI 1 "register_operand" ""))])]
+  "TARGET_H8300S
+   && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
+       || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
+       || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
+  "stm.l\\t%S0-%S1,@-er7"
+  [(set_attr "cc" "none")
+   (set_attr "length" "4")])
+
+(define_insn "*stm_h8300s_3"
+  [(parallel
+     [(set (reg:SI SP_REG)
+	   (plus:SI (reg:SI SP_REG) (const_int -12)))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
+	   (match_operand:SI 0 "register_operand" ""))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
+	   (match_operand:SI 1 "register_operand" ""))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
+	   (match_operand:SI 2 "register_operand" ""))])]
+  "TARGET_H8300S
+   && ((REGNO (operands[0]) == 0
+	&& REGNO (operands[1]) == 1
+	&& REGNO (operands[2]) == 2)
+       || (REGNO (operands[0]) == 4
+	   && REGNO (operands[1]) == 5
+	   && REGNO (operands[2]) == 6))"
+  "stm.l\\t%S0-%S2,@-er7"
+  [(set_attr "cc" "none")
+   (set_attr "length" "4")])
+
+(define_insn "*stm_h8300s_4"
+  [(parallel
+     [(set (reg:SI SP_REG)
+	   (plus:SI (reg:SI SP_REG) (const_int -16)))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
+	   (match_operand:SI 0 "register_operand" ""))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
+	   (match_operand:SI 1 "register_operand" ""))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
+	   (match_operand:SI 2 "register_operand" ""))
+      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
+	   (match_operand:SI 3 "register_operand" ""))])]
+  "TARGET_H8300S
+   && REGNO (operands[0]) == 0
+   && REGNO (operands[1]) == 1
+   && REGNO (operands[2]) == 2
+   && REGNO (operands[3]) == 3"
+  "stm.l\\t%S0-%S3,@-er7"
+  [(set_attr "cc" "none")
+   (set_attr "length" "4")])
+
+;; ----------------------------------------------------------------------
 ;; EXTEND INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
@@ -2484,3 +2546,105 @@
 		      (match_dup 1)))
       (clobber (match_dup 2))])]
   "")
+
+;; Convert a QImode push into an SImode push so that the
+;; define_peephole2 below can cram multiple pushes into one stm.l.
+
+(define_peephole2
+  [(parallel [(set (reg:SI SP_REG)
+                   (plus:SI (reg:SI SP_REG) (const_int -4)))
+              (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
+                   (match_operand:QI 0 "register_operand" ""))])]
+  "TARGET_H8300S"
+  [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_dup 0))]
+  "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
+
+;; Convert a HImode push into an SImode push so that the
+;; define_peephole2 below can cram multiple pushes into one stm.l.
+
+(define_peephole2
+  [(parallel [(set (reg:SI SP_REG)
+                   (plus:SI (reg:SI SP_REG) (const_int -4)))
+              (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
+                   (match_operand:HI 0 "register_operand" ""))])]
+  "TARGET_H8300S"
+  [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_dup 0))]
+  "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
+
+;; Cram four pushes into stm.l.
+
+(define_peephole2
+  [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 0 "register_operand" ""))
+   (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 1 "register_operand" ""))
+   (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 2 "register_operand" ""))
+   (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 3 "register_operand" ""))]
+  "TARGET_H8300S
+   && REGNO (operands[0]) == 0
+   && REGNO (operands[1]) == 1
+   && REGNO (operands[2]) == 2
+   && REGNO (operands[3]) == 3"
+  [(parallel [(set (reg:SI SP_REG)
+		   (plus:SI (reg:SI SP_REG)
+			    (const_int -16)))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
+		   (match_dup 0))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
+		   (match_dup 1))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
+		   (match_dup 2))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
+		   (match_dup 3))])]
+  "")
+
+;; Cram three pushes into stm.l.
+
+(define_peephole2
+  [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 0 "register_operand" ""))
+   (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 1 "register_operand" ""))
+   (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 2 "register_operand" ""))]
+  "TARGET_H8300S
+   && ((REGNO (operands[0]) == 0
+	&& REGNO (operands[1]) == 1
+	&& REGNO (operands[2]) == 2)
+       || (REGNO (operands[0]) == 4
+	   && REGNO (operands[1]) == 5
+	   && REGNO (operands[2]) == 6))"
+  [(parallel [(set (reg:SI SP_REG)
+		   (plus:SI (reg:SI SP_REG)
+			    (const_int -12)))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
+		   (match_dup 0))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
+		   (match_dup 1))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
+		   (match_dup 2))])]
+  "")
+
+;; Cram two pushes into stm.l.
+
+(define_peephole2
+  [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 0 "register_operand" ""))
+   (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+	(match_operand:SI 1 "register_operand" ""))]
+  "TARGET_H8300S
+   && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
+       || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
+       || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
+  [(parallel [(set (reg:SI SP_REG)
+		   (plus:SI (reg:SI SP_REG)
+			    (const_int -8)))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
+		   (match_dup 0))
+	      (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
+		   (match_dup 1))])]
+  "")