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| author | Jakub Jelinek <jakub@redhat.com> | 2021-02-03 09:04:26 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2021-02-03 09:10:28 +0100 |
| commit | 1b5572edb8caaed2f31a7235b8c58628da6bdb8f (patch) | |
| tree | 5988a7c0591e2730baa3069cf6d0b8f305547336 | |
| parent | 5e606ed90a1bed878071b6b5a3ef9b97b3d99838 (diff) | |
| download | gcc-1b5572edb8caaed2f31a7235b8c58628da6bdb8f.zip gcc-1b5572edb8caaed2f31a7235b8c58628da6bdb8f.tar.gz gcc-1b5572edb8caaed2f31a7235b8c58628da6bdb8f.tar.bz2 | |
i386: Remove V1DImode shift expanders [PR98287]
On Tue, Feb 02, 2021 at 02:23:55PM +0100, Richard Biener wrote:
> All I say is that the x86 target
> should either not advertise V1DF shifts or advertise the basic
> ops that reasonable simplification would expect to exist.
The backend has several V1?Imode shifts, but optab only for those V1DImode
ones:
grep '[la]sh[lr]v1[qhsdtox]' tmp-mddump.md
(define_insn ("mmx_ashlv1di3")
(define_insn ("mmx_lshrv1di3")
(define_insn ("avx512bw_ashlv1ti3")
(define_insn ("avx512bw_lshrv1ti3")
(define_insn ("sse2_ashlv1ti3")
(define_insn ("sse2_lshrv1ti3")
(define_expand ("ashlv1di3")
(define_expand ("lshrv1di3")
emit_insn (gen_sse2_lshrv1ti3 (tmp, gen_lowpart (V1TImode, operands[1]),
I think it has been introduced with
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89021#c13
Before we didn't have any V1DImode expanders (except mov/movmisalign, but
those are needed and are supplied for other V1??mode modes too).
This patch just removes the two V1DImode shift expanders with standard names.
2021-02-03 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/98287
* config/i386/mmx.md (<insn><mode>3): For shifts don't enable expander
for V1DImode.
* gcc.dg/pr98287.c: New test.
| -rw-r--r-- | gcc/config/i386/mmx.md | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr98287.c | 19 |
2 files changed, 22 insertions, 3 deletions
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index a6ddc710..9e5a4d1 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1528,9 +1528,9 @@ (set_attr "mode" "DI,TI,TI")]) (define_expand "<insn><mode>3" - [(set (match_operand:MMXMODE248 0 "register_operand") - (any_lshift:MMXMODE248 - (match_operand:MMXMODE248 1 "register_operand") + [(set (match_operand:MMXMODE24 0 "register_operand") + (any_lshift:MMXMODE24 + (match_operand:MMXMODE24 1 "register_operand") (match_operand:DI 2 "nonmemory_operand")))] "TARGET_MMX_WITH_SSE") diff --git a/gcc/testsuite/gcc.dg/pr98287.c b/gcc/testsuite/gcc.dg/pr98287.c new file mode 100644 index 0000000..0314428 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr98287.c @@ -0,0 +1,19 @@ +/* PR tree-optimization/98287 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-tree-ccp -fno-tree-forwprop -Wno-psabi -w" } */ + +typedef unsigned long __attribute__((__vector_size__ (8))) V; +V v; + +static __attribute__((noinline, noclone)) V +bar (unsigned short s) +{ + return v >> s << s | v >> s >> 63; +} + +unsigned long +foo (void) +{ + V x = bar (1); + return x[0]; +} |