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| author | Robin Dapp <rdapp@ventanamicro.com> | 2023-07-05 14:42:21 +0200 |
|---|---|---|
| committer | Robin Dapp <rdapp@ventanamicro.com> | 2023-07-05 15:54:51 +0200 |
| commit | 429905d809bbf2398bf666d65322b87ac7381e43 (patch) | |
| tree | 69caa752aa6928848fea4109d6b0d00b32d7088e | |
| parent | 34c614b7e9dcb52a23063680f3622c842a9712ec (diff) | |
| download | gcc-429905d809bbf2398bf666d65322b87ac7381e43.zip gcc-429905d809bbf2398bf666d65322b87ac7381e43.tar.gz gcc-429905d809bbf2398bf666d65322b87ac7381e43.tar.bz2 | |
RISC-V: Change truncate to float_truncate in narrowing patterns.
This fixes a bug in the autovect FP narrowing patterns which resulted in
a combine ICE. It would try to e.g. simplify a unary operation by
simplify_const_unary_operation which obviously expects a float_truncate
and not a truncate for a floating-point mode.
gcc/ChangeLog:
* config/riscv/autovec.md: Use float_truncate.
| -rw-r--r-- | gcc/config/riscv/autovec.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 4ab0e9f..0fc2bf5 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -473,7 +473,7 @@ ;; ------------------------------------------------------------------------- (define_insn_and_split "trunc<mode><v_double_trunc>2" [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vr") - (truncate:<V_DOUBLE_TRUNC> + (float_truncate:<V_DOUBLE_TRUNC> (match_operand:VWEXTF_ZVFHMIN 1 "register_operand" " vr")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" @@ -493,7 +493,7 @@ ;; ------------------------------------------------------------------------- (define_expand "trunc<mode><v_quad_trunc>2" [(set (match_operand:<V_QUAD_TRUNC> 0 "register_operand") - (truncate:<V_QUAD_TRUNC> + (float_truncate:<V_QUAD_TRUNC> (match_operand:VQEXTF 1 "register_operand")))] "TARGET_VECTOR && (TARGET_ZVFHMIN || TARGET_ZVFH)" { |